d1_pac/gpio/
pe_drv2.rs

1#[doc = "Register `pe_drv2` reader"]
2pub type R = crate::R<PE_DRV2_SPEC>;
3#[doc = "Register `pe_drv2` writer"]
4pub type W = crate::W<PE_DRV2_SPEC>;
5#[doc = "Field `pe_drv[16-17]` reader - PE Multi_Driving Select"]
6pub type PE_DRV_R = crate::FieldReader<PE_DRV_A>;
7#[doc = "PE Multi_Driving Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum PE_DRV_A {
11    #[doc = "0: `0`"]
12    L0 = 0,
13    #[doc = "1: `1`"]
14    L1 = 1,
15    #[doc = "2: `10`"]
16    L2 = 2,
17    #[doc = "3: `11`"]
18    L3 = 3,
19}
20impl From<PE_DRV_A> for u8 {
21    #[inline(always)]
22    fn from(variant: PE_DRV_A) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for PE_DRV_A {
27    type Ux = u8;
28}
29impl PE_DRV_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> PE_DRV_A {
33        match self.bits {
34            0 => PE_DRV_A::L0,
35            1 => PE_DRV_A::L1,
36            2 => PE_DRV_A::L2,
37            3 => PE_DRV_A::L3,
38            _ => unreachable!(),
39        }
40    }
41    #[doc = "`0`"]
42    #[inline(always)]
43    pub fn is_l0(&self) -> bool {
44        *self == PE_DRV_A::L0
45    }
46    #[doc = "`1`"]
47    #[inline(always)]
48    pub fn is_l1(&self) -> bool {
49        *self == PE_DRV_A::L1
50    }
51    #[doc = "`10`"]
52    #[inline(always)]
53    pub fn is_l2(&self) -> bool {
54        *self == PE_DRV_A::L2
55    }
56    #[doc = "`11`"]
57    #[inline(always)]
58    pub fn is_l3(&self) -> bool {
59        *self == PE_DRV_A::L3
60    }
61}
62#[doc = "Field `pe_drv[16-17]` writer - PE Multi_Driving Select"]
63pub type PE_DRV_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, PE_DRV_A>;
64impl<'a, REG> PE_DRV_W<'a, REG>
65where
66    REG: crate::Writable + crate::RegisterSpec,
67    REG::Ux: From<u8>,
68{
69    #[doc = "`0`"]
70    #[inline(always)]
71    pub fn l0(self) -> &'a mut crate::W<REG> {
72        self.variant(PE_DRV_A::L0)
73    }
74    #[doc = "`1`"]
75    #[inline(always)]
76    pub fn l1(self) -> &'a mut crate::W<REG> {
77        self.variant(PE_DRV_A::L1)
78    }
79    #[doc = "`10`"]
80    #[inline(always)]
81    pub fn l2(self) -> &'a mut crate::W<REG> {
82        self.variant(PE_DRV_A::L2)
83    }
84    #[doc = "`11`"]
85    #[inline(always)]
86    pub fn l3(self) -> &'a mut crate::W<REG> {
87        self.variant(PE_DRV_A::L3)
88    }
89}
90impl R {
91    #[doc = "PE Multi_Driving Select\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pe16_drv` field"]
92    #[inline(always)]
93    pub fn pe_drv(&self, n: u8) -> PE_DRV_R {
94        #[allow(clippy::no_effect)]
95        [(); 2][n as usize];
96        PE_DRV_R::new(((self.bits >> (n * 4)) & 3) as u8)
97    }
98    #[doc = "Bits 0:1 - PE Multi_Driving Select"]
99    #[inline(always)]
100    pub fn pe16_drv(&self) -> PE_DRV_R {
101        PE_DRV_R::new((self.bits & 3) as u8)
102    }
103    #[doc = "Bits 4:5 - PE Multi_Driving Select"]
104    #[inline(always)]
105    pub fn pe17_drv(&self) -> PE_DRV_R {
106        PE_DRV_R::new(((self.bits >> 4) & 3) as u8)
107    }
108}
109impl W {
110    #[doc = "PE Multi_Driving Select\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pe16_drv` field"]
111    #[inline(always)]
112    #[must_use]
113    pub fn pe_drv(&mut self, n: u8) -> PE_DRV_W<PE_DRV2_SPEC> {
114        #[allow(clippy::no_effect)]
115        [(); 2][n as usize];
116        PE_DRV_W::new(self, n * 4)
117    }
118    #[doc = "Bits 0:1 - PE Multi_Driving Select"]
119    #[inline(always)]
120    #[must_use]
121    pub fn pe16_drv(&mut self) -> PE_DRV_W<PE_DRV2_SPEC> {
122        PE_DRV_W::new(self, 0)
123    }
124    #[doc = "Bits 4:5 - PE Multi_Driving Select"]
125    #[inline(always)]
126    #[must_use]
127    pub fn pe17_drv(&mut self) -> PE_DRV_W<PE_DRV2_SPEC> {
128        PE_DRV_W::new(self, 4)
129    }
130    #[doc = r" Writes raw bits to the register."]
131    #[doc = r""]
132    #[doc = r" # Safety"]
133    #[doc = r""]
134    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
135    #[inline(always)]
136    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
137        self.bits = bits;
138        self
139    }
140}
141#[doc = "PE Multi_Driving Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pe_drv2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pe_drv2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
142pub struct PE_DRV2_SPEC;
143impl crate::RegisterSpec for PE_DRV2_SPEC {
144    type Ux = u32;
145}
146#[doc = "`read()` method returns [`pe_drv2::R`](R) reader structure"]
147impl crate::Readable for PE_DRV2_SPEC {}
148#[doc = "`write(|w| ..)` method takes [`pe_drv2::W`](W) writer structure"]
149impl crate::Writable for PE_DRV2_SPEC {
150    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
151    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
152}
153#[doc = "`reset()` method sets pe_drv2 to value 0"]
154impl crate::Resettable for PE_DRV2_SPEC {
155    const RESET_VALUE: Self::Ux = 0;
156}
d1_pac/gpio/pe_drv2.rs

d1_pac/gpio/
pe_drv2.rs
