d1_pac/gpio/
pe_cfg2.rs

1#[doc = "Register `pe_cfg2` reader"]
2pub type R = crate::R<PE_CFG2_SPEC>;
3#[doc = "Register `pe_cfg2` writer"]
4pub type W = crate::W<PE_CFG2_SPEC>;
5#[doc = "Field `pe16_select` reader - PE16 Select"]
6pub type PE16_SELECT_R = crate::FieldReader<PE16_SELECT_A>;
7#[doc = "PE16 Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum PE16_SELECT_A {
11    #[doc = "0: `0`"]
12    INPUT = 0,
13    #[doc = "2: `10`"]
14    TWI3_SCK = 2,
15    #[doc = "4: `100`"]
16    PWM7 = 4,
17    #[doc = "6: `110`"]
18    DMIC_DATA0 = 6,
19    #[doc = "14: `1110`"]
20    PE_EINT16 = 14,
21    #[doc = "1: `1`"]
22    OUTPUT = 1,
23    #[doc = "3: `11`"]
24    D_JTAG_DO = 3,
25    #[doc = "5: `101`"]
26    I2S0_BCLK = 5,
27    #[doc = "15: `1111`"]
28    IO_DISABLE = 15,
29}
30impl From<PE16_SELECT_A> for u8 {
31    #[inline(always)]
32    fn from(variant: PE16_SELECT_A) -> Self {
33        variant as _
34    }
35}
36impl crate::FieldSpec for PE16_SELECT_A {
37    type Ux = u8;
38}
39impl PE16_SELECT_R {
40    #[doc = "Get enumerated values variant"]
41    #[inline(always)]
42    pub const fn variant(&self) -> Option<PE16_SELECT_A> {
43        match self.bits {
44            0 => Some(PE16_SELECT_A::INPUT),
45            2 => Some(PE16_SELECT_A::TWI3_SCK),
46            4 => Some(PE16_SELECT_A::PWM7),
47            6 => Some(PE16_SELECT_A::DMIC_DATA0),
48            14 => Some(PE16_SELECT_A::PE_EINT16),
49            1 => Some(PE16_SELECT_A::OUTPUT),
50            3 => Some(PE16_SELECT_A::D_JTAG_DO),
51            5 => Some(PE16_SELECT_A::I2S0_BCLK),
52            15 => Some(PE16_SELECT_A::IO_DISABLE),
53            _ => None,
54        }
55    }
56    #[doc = "`0`"]
57    #[inline(always)]
58    pub fn is_input(&self) -> bool {
59        *self == PE16_SELECT_A::INPUT
60    }
61    #[doc = "`10`"]
62    #[inline(always)]
63    pub fn is_twi3_sck(&self) -> bool {
64        *self == PE16_SELECT_A::TWI3_SCK
65    }
66    #[doc = "`100`"]
67    #[inline(always)]
68    pub fn is_pwm7(&self) -> bool {
69        *self == PE16_SELECT_A::PWM7
70    }
71    #[doc = "`110`"]
72    #[inline(always)]
73    pub fn is_dmic_data0(&self) -> bool {
74        *self == PE16_SELECT_A::DMIC_DATA0
75    }
76    #[doc = "`1110`"]
77    #[inline(always)]
78    pub fn is_pe_eint16(&self) -> bool {
79        *self == PE16_SELECT_A::PE_EINT16
80    }
81    #[doc = "`1`"]
82    #[inline(always)]
83    pub fn is_output(&self) -> bool {
84        *self == PE16_SELECT_A::OUTPUT
85    }
86    #[doc = "`11`"]
87    #[inline(always)]
88    pub fn is_d_jtag_do(&self) -> bool {
89        *self == PE16_SELECT_A::D_JTAG_DO
90    }
91    #[doc = "`101`"]
92    #[inline(always)]
93    pub fn is_i2s0_bclk(&self) -> bool {
94        *self == PE16_SELECT_A::I2S0_BCLK
95    }
96    #[doc = "`1111`"]
97    #[inline(always)]
98    pub fn is_io_disable(&self) -> bool {
99        *self == PE16_SELECT_A::IO_DISABLE
100    }
101}
102#[doc = "Field `pe16_select` writer - PE16 Select"]
103pub type PE16_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE16_SELECT_A>;
104impl<'a, REG> PE16_SELECT_W<'a, REG>
105where
106    REG: crate::Writable + crate::RegisterSpec,
107    REG::Ux: From<u8>,
108{
109    #[doc = "`0`"]
110    #[inline(always)]
111    pub fn input(self) -> &'a mut crate::W<REG> {
112        self.variant(PE16_SELECT_A::INPUT)
113    }
114    #[doc = "`10`"]
115    #[inline(always)]
116    pub fn twi3_sck(self) -> &'a mut crate::W<REG> {
117        self.variant(PE16_SELECT_A::TWI3_SCK)
118    }
119    #[doc = "`100`"]
120    #[inline(always)]
121    pub fn pwm7(self) -> &'a mut crate::W<REG> {
122        self.variant(PE16_SELECT_A::PWM7)
123    }
124    #[doc = "`110`"]
125    #[inline(always)]
126    pub fn dmic_data0(self) -> &'a mut crate::W<REG> {
127        self.variant(PE16_SELECT_A::DMIC_DATA0)
128    }
129    #[doc = "`1110`"]
130    #[inline(always)]
131    pub fn pe_eint16(self) -> &'a mut crate::W<REG> {
132        self.variant(PE16_SELECT_A::PE_EINT16)
133    }
134    #[doc = "`1`"]
135    #[inline(always)]
136    pub fn output(self) -> &'a mut crate::W<REG> {
137        self.variant(PE16_SELECT_A::OUTPUT)
138    }
139    #[doc = "`11`"]
140    #[inline(always)]
141    pub fn d_jtag_do(self) -> &'a mut crate::W<REG> {
142        self.variant(PE16_SELECT_A::D_JTAG_DO)
143    }
144    #[doc = "`101`"]
145    #[inline(always)]
146    pub fn i2s0_bclk(self) -> &'a mut crate::W<REG> {
147        self.variant(PE16_SELECT_A::I2S0_BCLK)
148    }
149    #[doc = "`1111`"]
150    #[inline(always)]
151    pub fn io_disable(self) -> &'a mut crate::W<REG> {
152        self.variant(PE16_SELECT_A::IO_DISABLE)
153    }
154}
155#[doc = "Field `pe17_select` reader - PE17 Select"]
156pub type PE17_SELECT_R = crate::FieldReader<PE17_SELECT_A>;
157#[doc = "PE17 Select\n\nValue on reset: 0"]
158#[derive(Clone, Copy, Debug, PartialEq, Eq)]
159#[repr(u8)]
160pub enum PE17_SELECT_A {
161    #[doc = "0: `0`"]
162    INPUT = 0,
163    #[doc = "2: `10`"]
164    TWI3_SDA = 2,
165    #[doc = "4: `100`"]
166    IR_TX = 4,
167    #[doc = "6: `110`"]
168    DMIC_CLK = 6,
169    #[doc = "14: `1110`"]
170    PE_EINT17 = 14,
171    #[doc = "1: `1`"]
172    OUTPUT = 1,
173    #[doc = "3: `11`"]
174    D_JTAG_CK = 3,
175    #[doc = "5: `101`"]
176    I2S0_MCLK = 5,
177    #[doc = "15: `1111`"]
178    IO_DISABLE = 15,
179}
180impl From<PE17_SELECT_A> for u8 {
181    #[inline(always)]
182    fn from(variant: PE17_SELECT_A) -> Self {
183        variant as _
184    }
185}
186impl crate::FieldSpec for PE17_SELECT_A {
187    type Ux = u8;
188}
189impl PE17_SELECT_R {
190    #[doc = "Get enumerated values variant"]
191    #[inline(always)]
192    pub const fn variant(&self) -> Option<PE17_SELECT_A> {
193        match self.bits {
194            0 => Some(PE17_SELECT_A::INPUT),
195            2 => Some(PE17_SELECT_A::TWI3_SDA),
196            4 => Some(PE17_SELECT_A::IR_TX),
197            6 => Some(PE17_SELECT_A::DMIC_CLK),
198            14 => Some(PE17_SELECT_A::PE_EINT17),
199            1 => Some(PE17_SELECT_A::OUTPUT),
200            3 => Some(PE17_SELECT_A::D_JTAG_CK),
201            5 => Some(PE17_SELECT_A::I2S0_MCLK),
202            15 => Some(PE17_SELECT_A::IO_DISABLE),
203            _ => None,
204        }
205    }
206    #[doc = "`0`"]
207    #[inline(always)]
208    pub fn is_input(&self) -> bool {
209        *self == PE17_SELECT_A::INPUT
210    }
211    #[doc = "`10`"]
212    #[inline(always)]
213    pub fn is_twi3_sda(&self) -> bool {
214        *self == PE17_SELECT_A::TWI3_SDA
215    }
216    #[doc = "`100`"]
217    #[inline(always)]
218    pub fn is_ir_tx(&self) -> bool {
219        *self == PE17_SELECT_A::IR_TX
220    }
221    #[doc = "`110`"]
222    #[inline(always)]
223    pub fn is_dmic_clk(&self) -> bool {
224        *self == PE17_SELECT_A::DMIC_CLK
225    }
226    #[doc = "`1110`"]
227    #[inline(always)]
228    pub fn is_pe_eint17(&self) -> bool {
229        *self == PE17_SELECT_A::PE_EINT17
230    }
231    #[doc = "`1`"]
232    #[inline(always)]
233    pub fn is_output(&self) -> bool {
234        *self == PE17_SELECT_A::OUTPUT
235    }
236    #[doc = "`11`"]
237    #[inline(always)]
238    pub fn is_d_jtag_ck(&self) -> bool {
239        *self == PE17_SELECT_A::D_JTAG_CK
240    }
241    #[doc = "`101`"]
242    #[inline(always)]
243    pub fn is_i2s0_mclk(&self) -> bool {
244        *self == PE17_SELECT_A::I2S0_MCLK
245    }
246    #[doc = "`1111`"]
247    #[inline(always)]
248    pub fn is_io_disable(&self) -> bool {
249        *self == PE17_SELECT_A::IO_DISABLE
250    }
251}
252#[doc = "Field `pe17_select` writer - PE17 Select"]
253pub type PE17_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE17_SELECT_A>;
254impl<'a, REG> PE17_SELECT_W<'a, REG>
255where
256    REG: crate::Writable + crate::RegisterSpec,
257    REG::Ux: From<u8>,
258{
259    #[doc = "`0`"]
260    #[inline(always)]
261    pub fn input(self) -> &'a mut crate::W<REG> {
262        self.variant(PE17_SELECT_A::INPUT)
263    }
264    #[doc = "`10`"]
265    #[inline(always)]
266    pub fn twi3_sda(self) -> &'a mut crate::W<REG> {
267        self.variant(PE17_SELECT_A::TWI3_SDA)
268    }
269    #[doc = "`100`"]
270    #[inline(always)]
271    pub fn ir_tx(self) -> &'a mut crate::W<REG> {
272        self.variant(PE17_SELECT_A::IR_TX)
273    }
274    #[doc = "`110`"]
275    #[inline(always)]
276    pub fn dmic_clk(self) -> &'a mut crate::W<REG> {
277        self.variant(PE17_SELECT_A::DMIC_CLK)
278    }
279    #[doc = "`1110`"]
280    #[inline(always)]
281    pub fn pe_eint17(self) -> &'a mut crate::W<REG> {
282        self.variant(PE17_SELECT_A::PE_EINT17)
283    }
284    #[doc = "`1`"]
285    #[inline(always)]
286    pub fn output(self) -> &'a mut crate::W<REG> {
287        self.variant(PE17_SELECT_A::OUTPUT)
288    }
289    #[doc = "`11`"]
290    #[inline(always)]
291    pub fn d_jtag_ck(self) -> &'a mut crate::W<REG> {
292        self.variant(PE17_SELECT_A::D_JTAG_CK)
293    }
294    #[doc = "`101`"]
295    #[inline(always)]
296    pub fn i2s0_mclk(self) -> &'a mut crate::W<REG> {
297        self.variant(PE17_SELECT_A::I2S0_MCLK)
298    }
299    #[doc = "`1111`"]
300    #[inline(always)]
301    pub fn io_disable(self) -> &'a mut crate::W<REG> {
302        self.variant(PE17_SELECT_A::IO_DISABLE)
303    }
304}
305impl R {
306    #[doc = "Bits 0:3 - PE16 Select"]
307    #[inline(always)]
308    pub fn pe16_select(&self) -> PE16_SELECT_R {
309        PE16_SELECT_R::new((self.bits & 0x0f) as u8)
310    }
311    #[doc = "Bits 4:7 - PE17 Select"]
312    #[inline(always)]
313    pub fn pe17_select(&self) -> PE17_SELECT_R {
314        PE17_SELECT_R::new(((self.bits >> 4) & 0x0f) as u8)
315    }
316}
317impl W {
318    #[doc = "Bits 0:3 - PE16 Select"]
319    #[inline(always)]
320    #[must_use]
321    pub fn pe16_select(&mut self) -> PE16_SELECT_W<PE_CFG2_SPEC> {
322        PE16_SELECT_W::new(self, 0)
323    }
324    #[doc = "Bits 4:7 - PE17 Select"]
325    #[inline(always)]
326    #[must_use]
327    pub fn pe17_select(&mut self) -> PE17_SELECT_W<PE_CFG2_SPEC> {
328        PE17_SELECT_W::new(self, 4)
329    }
330    #[doc = r" Writes raw bits to the register."]
331    #[doc = r""]
332    #[doc = r" # Safety"]
333    #[doc = r""]
334    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
335    #[inline(always)]
336    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
337        self.bits = bits;
338        self
339    }
340}
341#[doc = "PE Configure Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pe_cfg2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pe_cfg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
342pub struct PE_CFG2_SPEC;
343impl crate::RegisterSpec for PE_CFG2_SPEC {
344    type Ux = u32;
345}
346#[doc = "`read()` method returns [`pe_cfg2::R`](R) reader structure"]
347impl crate::Readable for PE_CFG2_SPEC {}
348#[doc = "`write(|w| ..)` method takes [`pe_cfg2::W`](W) writer structure"]
349impl crate::Writable for PE_CFG2_SPEC {
350    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
351    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
352}
353#[doc = "`reset()` method sets pe_cfg2 to value 0"]
354impl crate::Resettable for PE_CFG2_SPEC {
355    const RESET_VALUE: Self::Ux = 0;
356}
d1_pac/gpio/pe_cfg2.rs

d1_pac/gpio/
pe_cfg2.rs
