1#[doc = "Register `pe_cfg1` reader"]
2pub type R = crate::R<PE_CFG1_SPEC>;
3#[doc = "Register `pe_cfg1` writer"]
4pub type W = crate::W<PE_CFG1_SPEC>;
5#[doc = "Field `pe8_select` reader - PE8 Select"]
6pub type PE8_SELECT_R = crate::FieldReader<PE8_SELECT_A>;
7#[doc = "PE8 Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum PE8_SELECT_A {
11 #[doc = "0: `0`"]
12 INPUT = 0,
13 #[doc = "2: `10`"]
14 NCSI0_D4 = 2,
15 #[doc = "4: `100`"]
16 PWM2 = 4,
17 #[doc = "6: `110`"]
18 JTAG_MS = 6,
19 #[doc = "8: `1000`"]
20 MDC = 8,
21 #[doc = "14: `1110`"]
22 PE_EINT8 = 14,
23 #[doc = "1: `1`"]
24 OUTPUT = 1,
25 #[doc = "3: `11`"]
26 UART1_RTS = 3,
27 #[doc = "5: `101`"]
28 UART3_TX = 5,
29 #[doc = "15: `1111`"]
30 IO_DISABLE = 15,
31}
32impl From<PE8_SELECT_A> for u8 {
33 #[inline(always)]
34 fn from(variant: PE8_SELECT_A) -> Self {
35 variant as _
36 }
37}
38impl crate::FieldSpec for PE8_SELECT_A {
39 type Ux = u8;
40}
41impl PE8_SELECT_R {
42 #[doc = "Get enumerated values variant"]
43 #[inline(always)]
44 pub const fn variant(&self) -> Option<PE8_SELECT_A> {
45 match self.bits {
46 0 => Some(PE8_SELECT_A::INPUT),
47 2 => Some(PE8_SELECT_A::NCSI0_D4),
48 4 => Some(PE8_SELECT_A::PWM2),
49 6 => Some(PE8_SELECT_A::JTAG_MS),
50 8 => Some(PE8_SELECT_A::MDC),
51 14 => Some(PE8_SELECT_A::PE_EINT8),
52 1 => Some(PE8_SELECT_A::OUTPUT),
53 3 => Some(PE8_SELECT_A::UART1_RTS),
54 5 => Some(PE8_SELECT_A::UART3_TX),
55 15 => Some(PE8_SELECT_A::IO_DISABLE),
56 _ => None,
57 }
58 }
59 #[doc = "`0`"]
60 #[inline(always)]
61 pub fn is_input(&self) -> bool {
62 *self == PE8_SELECT_A::INPUT
63 }
64 #[doc = "`10`"]
65 #[inline(always)]
66 pub fn is_ncsi0_d4(&self) -> bool {
67 *self == PE8_SELECT_A::NCSI0_D4
68 }
69 #[doc = "`100`"]
70 #[inline(always)]
71 pub fn is_pwm2(&self) -> bool {
72 *self == PE8_SELECT_A::PWM2
73 }
74 #[doc = "`110`"]
75 #[inline(always)]
76 pub fn is_jtag_ms(&self) -> bool {
77 *self == PE8_SELECT_A::JTAG_MS
78 }
79 #[doc = "`1000`"]
80 #[inline(always)]
81 pub fn is_mdc(&self) -> bool {
82 *self == PE8_SELECT_A::MDC
83 }
84 #[doc = "`1110`"]
85 #[inline(always)]
86 pub fn is_pe_eint8(&self) -> bool {
87 *self == PE8_SELECT_A::PE_EINT8
88 }
89 #[doc = "`1`"]
90 #[inline(always)]
91 pub fn is_output(&self) -> bool {
92 *self == PE8_SELECT_A::OUTPUT
93 }
94 #[doc = "`11`"]
95 #[inline(always)]
96 pub fn is_uart1_rts(&self) -> bool {
97 *self == PE8_SELECT_A::UART1_RTS
98 }
99 #[doc = "`101`"]
100 #[inline(always)]
101 pub fn is_uart3_tx(&self) -> bool {
102 *self == PE8_SELECT_A::UART3_TX
103 }
104 #[doc = "`1111`"]
105 #[inline(always)]
106 pub fn is_io_disable(&self) -> bool {
107 *self == PE8_SELECT_A::IO_DISABLE
108 }
109}
110#[doc = "Field `pe8_select` writer - PE8 Select"]
111pub type PE8_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE8_SELECT_A>;
112impl<'a, REG> PE8_SELECT_W<'a, REG>
113where
114 REG: crate::Writable + crate::RegisterSpec,
115 REG::Ux: From<u8>,
116{
117 #[doc = "`0`"]
118 #[inline(always)]
119 pub fn input(self) -> &'a mut crate::W<REG> {
120 self.variant(PE8_SELECT_A::INPUT)
121 }
122 #[doc = "`10`"]
123 #[inline(always)]
124 pub fn ncsi0_d4(self) -> &'a mut crate::W<REG> {
125 self.variant(PE8_SELECT_A::NCSI0_D4)
126 }
127 #[doc = "`100`"]
128 #[inline(always)]
129 pub fn pwm2(self) -> &'a mut crate::W<REG> {
130 self.variant(PE8_SELECT_A::PWM2)
131 }
132 #[doc = "`110`"]
133 #[inline(always)]
134 pub fn jtag_ms(self) -> &'a mut crate::W<REG> {
135 self.variant(PE8_SELECT_A::JTAG_MS)
136 }
137 #[doc = "`1000`"]
138 #[inline(always)]
139 pub fn mdc(self) -> &'a mut crate::W<REG> {
140 self.variant(PE8_SELECT_A::MDC)
141 }
142 #[doc = "`1110`"]
143 #[inline(always)]
144 pub fn pe_eint8(self) -> &'a mut crate::W<REG> {
145 self.variant(PE8_SELECT_A::PE_EINT8)
146 }
147 #[doc = "`1`"]
148 #[inline(always)]
149 pub fn output(self) -> &'a mut crate::W<REG> {
150 self.variant(PE8_SELECT_A::OUTPUT)
151 }
152 #[doc = "`11`"]
153 #[inline(always)]
154 pub fn uart1_rts(self) -> &'a mut crate::W<REG> {
155 self.variant(PE8_SELECT_A::UART1_RTS)
156 }
157 #[doc = "`101`"]
158 #[inline(always)]
159 pub fn uart3_tx(self) -> &'a mut crate::W<REG> {
160 self.variant(PE8_SELECT_A::UART3_TX)
161 }
162 #[doc = "`1111`"]
163 #[inline(always)]
164 pub fn io_disable(self) -> &'a mut crate::W<REG> {
165 self.variant(PE8_SELECT_A::IO_DISABLE)
166 }
167}
168#[doc = "Field `pe9_select` reader - PE9 Select"]
169pub type PE9_SELECT_R = crate::FieldReader<PE9_SELECT_A>;
170#[doc = "PE9 Select\n\nValue on reset: 0"]
171#[derive(Clone, Copy, Debug, PartialEq, Eq)]
172#[repr(u8)]
173pub enum PE9_SELECT_A {
174 #[doc = "0: `0`"]
175 INPUT = 0,
176 #[doc = "2: `10`"]
177 NCSI0_D5 = 2,
178 #[doc = "4: `100`"]
179 PWM3 = 4,
180 #[doc = "6: `110`"]
181 JTAG_DI = 6,
182 #[doc = "8: `1000`"]
183 MDIO = 8,
184 #[doc = "14: `1110`"]
185 PE_EINT9 = 14,
186 #[doc = "1: `1`"]
187 OUTPUT = 1,
188 #[doc = "3: `11`"]
189 UART1_CTS = 3,
190 #[doc = "5: `101`"]
191 UART3_RX = 5,
192 #[doc = "15: `1111`"]
193 IO_DISABLE = 15,
194}
195impl From<PE9_SELECT_A> for u8 {
196 #[inline(always)]
197 fn from(variant: PE9_SELECT_A) -> Self {
198 variant as _
199 }
200}
201impl crate::FieldSpec for PE9_SELECT_A {
202 type Ux = u8;
203}
204impl PE9_SELECT_R {
205 #[doc = "Get enumerated values variant"]
206 #[inline(always)]
207 pub const fn variant(&self) -> Option<PE9_SELECT_A> {
208 match self.bits {
209 0 => Some(PE9_SELECT_A::INPUT),
210 2 => Some(PE9_SELECT_A::NCSI0_D5),
211 4 => Some(PE9_SELECT_A::PWM3),
212 6 => Some(PE9_SELECT_A::JTAG_DI),
213 8 => Some(PE9_SELECT_A::MDIO),
214 14 => Some(PE9_SELECT_A::PE_EINT9),
215 1 => Some(PE9_SELECT_A::OUTPUT),
216 3 => Some(PE9_SELECT_A::UART1_CTS),
217 5 => Some(PE9_SELECT_A::UART3_RX),
218 15 => Some(PE9_SELECT_A::IO_DISABLE),
219 _ => None,
220 }
221 }
222 #[doc = "`0`"]
223 #[inline(always)]
224 pub fn is_input(&self) -> bool {
225 *self == PE9_SELECT_A::INPUT
226 }
227 #[doc = "`10`"]
228 #[inline(always)]
229 pub fn is_ncsi0_d5(&self) -> bool {
230 *self == PE9_SELECT_A::NCSI0_D5
231 }
232 #[doc = "`100`"]
233 #[inline(always)]
234 pub fn is_pwm3(&self) -> bool {
235 *self == PE9_SELECT_A::PWM3
236 }
237 #[doc = "`110`"]
238 #[inline(always)]
239 pub fn is_jtag_di(&self) -> bool {
240 *self == PE9_SELECT_A::JTAG_DI
241 }
242 #[doc = "`1000`"]
243 #[inline(always)]
244 pub fn is_mdio(&self) -> bool {
245 *self == PE9_SELECT_A::MDIO
246 }
247 #[doc = "`1110`"]
248 #[inline(always)]
249 pub fn is_pe_eint9(&self) -> bool {
250 *self == PE9_SELECT_A::PE_EINT9
251 }
252 #[doc = "`1`"]
253 #[inline(always)]
254 pub fn is_output(&self) -> bool {
255 *self == PE9_SELECT_A::OUTPUT
256 }
257 #[doc = "`11`"]
258 #[inline(always)]
259 pub fn is_uart1_cts(&self) -> bool {
260 *self == PE9_SELECT_A::UART1_CTS
261 }
262 #[doc = "`101`"]
263 #[inline(always)]
264 pub fn is_uart3_rx(&self) -> bool {
265 *self == PE9_SELECT_A::UART3_RX
266 }
267 #[doc = "`1111`"]
268 #[inline(always)]
269 pub fn is_io_disable(&self) -> bool {
270 *self == PE9_SELECT_A::IO_DISABLE
271 }
272}
273#[doc = "Field `pe9_select` writer - PE9 Select"]
274pub type PE9_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE9_SELECT_A>;
275impl<'a, REG> PE9_SELECT_W<'a, REG>
276where
277 REG: crate::Writable + crate::RegisterSpec,
278 REG::Ux: From<u8>,
279{
280 #[doc = "`0`"]
281 #[inline(always)]
282 pub fn input(self) -> &'a mut crate::W<REG> {
283 self.variant(PE9_SELECT_A::INPUT)
284 }
285 #[doc = "`10`"]
286 #[inline(always)]
287 pub fn ncsi0_d5(self) -> &'a mut crate::W<REG> {
288 self.variant(PE9_SELECT_A::NCSI0_D5)
289 }
290 #[doc = "`100`"]
291 #[inline(always)]
292 pub fn pwm3(self) -> &'a mut crate::W<REG> {
293 self.variant(PE9_SELECT_A::PWM3)
294 }
295 #[doc = "`110`"]
296 #[inline(always)]
297 pub fn jtag_di(self) -> &'a mut crate::W<REG> {
298 self.variant(PE9_SELECT_A::JTAG_DI)
299 }
300 #[doc = "`1000`"]
301 #[inline(always)]
302 pub fn mdio(self) -> &'a mut crate::W<REG> {
303 self.variant(PE9_SELECT_A::MDIO)
304 }
305 #[doc = "`1110`"]
306 #[inline(always)]
307 pub fn pe_eint9(self) -> &'a mut crate::W<REG> {
308 self.variant(PE9_SELECT_A::PE_EINT9)
309 }
310 #[doc = "`1`"]
311 #[inline(always)]
312 pub fn output(self) -> &'a mut crate::W<REG> {
313 self.variant(PE9_SELECT_A::OUTPUT)
314 }
315 #[doc = "`11`"]
316 #[inline(always)]
317 pub fn uart1_cts(self) -> &'a mut crate::W<REG> {
318 self.variant(PE9_SELECT_A::UART1_CTS)
319 }
320 #[doc = "`101`"]
321 #[inline(always)]
322 pub fn uart3_rx(self) -> &'a mut crate::W<REG> {
323 self.variant(PE9_SELECT_A::UART3_RX)
324 }
325 #[doc = "`1111`"]
326 #[inline(always)]
327 pub fn io_disable(self) -> &'a mut crate::W<REG> {
328 self.variant(PE9_SELECT_A::IO_DISABLE)
329 }
330}
331#[doc = "Field `pe10_select` reader - PE10 Select"]
332pub type PE10_SELECT_R = crate::FieldReader<PE10_SELECT_A>;
333#[doc = "PE10 Select\n\nValue on reset: 0"]
334#[derive(Clone, Copy, Debug, PartialEq, Eq)]
335#[repr(u8)]
336pub enum PE10_SELECT_A {
337 #[doc = "0: `0`"]
338 INPUT = 0,
339 #[doc = "2: `10`"]
340 NCSI0_D6 = 2,
341 #[doc = "4: `100`"]
342 PWM4 = 4,
343 #[doc = "6: `110`"]
344 JTAG_DO = 6,
345 #[doc = "8: `1000`"]
346 EPHY_25M = 8,
347 #[doc = "14: `1110`"]
348 PE_EINT10 = 14,
349 #[doc = "1: `1`"]
350 OUTPUT = 1,
351 #[doc = "3: `11`"]
352 UART1_TX = 3,
353 #[doc = "5: `101`"]
354 IR_RX = 5,
355 #[doc = "15: `1111`"]
356 IO_DISABLE = 15,
357}
358impl From<PE10_SELECT_A> for u8 {
359 #[inline(always)]
360 fn from(variant: PE10_SELECT_A) -> Self {
361 variant as _
362 }
363}
364impl crate::FieldSpec for PE10_SELECT_A {
365 type Ux = u8;
366}
367impl PE10_SELECT_R {
368 #[doc = "Get enumerated values variant"]
369 #[inline(always)]
370 pub const fn variant(&self) -> Option<PE10_SELECT_A> {
371 match self.bits {
372 0 => Some(PE10_SELECT_A::INPUT),
373 2 => Some(PE10_SELECT_A::NCSI0_D6),
374 4 => Some(PE10_SELECT_A::PWM4),
375 6 => Some(PE10_SELECT_A::JTAG_DO),
376 8 => Some(PE10_SELECT_A::EPHY_25M),
377 14 => Some(PE10_SELECT_A::PE_EINT10),
378 1 => Some(PE10_SELECT_A::OUTPUT),
379 3 => Some(PE10_SELECT_A::UART1_TX),
380 5 => Some(PE10_SELECT_A::IR_RX),
381 15 => Some(PE10_SELECT_A::IO_DISABLE),
382 _ => None,
383 }
384 }
385 #[doc = "`0`"]
386 #[inline(always)]
387 pub fn is_input(&self) -> bool {
388 *self == PE10_SELECT_A::INPUT
389 }
390 #[doc = "`10`"]
391 #[inline(always)]
392 pub fn is_ncsi0_d6(&self) -> bool {
393 *self == PE10_SELECT_A::NCSI0_D6
394 }
395 #[doc = "`100`"]
396 #[inline(always)]
397 pub fn is_pwm4(&self) -> bool {
398 *self == PE10_SELECT_A::PWM4
399 }
400 #[doc = "`110`"]
401 #[inline(always)]
402 pub fn is_jtag_do(&self) -> bool {
403 *self == PE10_SELECT_A::JTAG_DO
404 }
405 #[doc = "`1000`"]
406 #[inline(always)]
407 pub fn is_ephy_25m(&self) -> bool {
408 *self == PE10_SELECT_A::EPHY_25M
409 }
410 #[doc = "`1110`"]
411 #[inline(always)]
412 pub fn is_pe_eint10(&self) -> bool {
413 *self == PE10_SELECT_A::PE_EINT10
414 }
415 #[doc = "`1`"]
416 #[inline(always)]
417 pub fn is_output(&self) -> bool {
418 *self == PE10_SELECT_A::OUTPUT
419 }
420 #[doc = "`11`"]
421 #[inline(always)]
422 pub fn is_uart1_tx(&self) -> bool {
423 *self == PE10_SELECT_A::UART1_TX
424 }
425 #[doc = "`101`"]
426 #[inline(always)]
427 pub fn is_ir_rx(&self) -> bool {
428 *self == PE10_SELECT_A::IR_RX
429 }
430 #[doc = "`1111`"]
431 #[inline(always)]
432 pub fn is_io_disable(&self) -> bool {
433 *self == PE10_SELECT_A::IO_DISABLE
434 }
435}
436#[doc = "Field `pe10_select` writer - PE10 Select"]
437pub type PE10_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE10_SELECT_A>;
438impl<'a, REG> PE10_SELECT_W<'a, REG>
439where
440 REG: crate::Writable + crate::RegisterSpec,
441 REG::Ux: From<u8>,
442{
443 #[doc = "`0`"]
444 #[inline(always)]
445 pub fn input(self) -> &'a mut crate::W<REG> {
446 self.variant(PE10_SELECT_A::INPUT)
447 }
448 #[doc = "`10`"]
449 #[inline(always)]
450 pub fn ncsi0_d6(self) -> &'a mut crate::W<REG> {
451 self.variant(PE10_SELECT_A::NCSI0_D6)
452 }
453 #[doc = "`100`"]
454 #[inline(always)]
455 pub fn pwm4(self) -> &'a mut crate::W<REG> {
456 self.variant(PE10_SELECT_A::PWM4)
457 }
458 #[doc = "`110`"]
459 #[inline(always)]
460 pub fn jtag_do(self) -> &'a mut crate::W<REG> {
461 self.variant(PE10_SELECT_A::JTAG_DO)
462 }
463 #[doc = "`1000`"]
464 #[inline(always)]
465 pub fn ephy_25m(self) -> &'a mut crate::W<REG> {
466 self.variant(PE10_SELECT_A::EPHY_25M)
467 }
468 #[doc = "`1110`"]
469 #[inline(always)]
470 pub fn pe_eint10(self) -> &'a mut crate::W<REG> {
471 self.variant(PE10_SELECT_A::PE_EINT10)
472 }
473 #[doc = "`1`"]
474 #[inline(always)]
475 pub fn output(self) -> &'a mut crate::W<REG> {
476 self.variant(PE10_SELECT_A::OUTPUT)
477 }
478 #[doc = "`11`"]
479 #[inline(always)]
480 pub fn uart1_tx(self) -> &'a mut crate::W<REG> {
481 self.variant(PE10_SELECT_A::UART1_TX)
482 }
483 #[doc = "`101`"]
484 #[inline(always)]
485 pub fn ir_rx(self) -> &'a mut crate::W<REG> {
486 self.variant(PE10_SELECT_A::IR_RX)
487 }
488 #[doc = "`1111`"]
489 #[inline(always)]
490 pub fn io_disable(self) -> &'a mut crate::W<REG> {
491 self.variant(PE10_SELECT_A::IO_DISABLE)
492 }
493}
494#[doc = "Field `pe11_select` reader - PE11 Select"]
495pub type PE11_SELECT_R = crate::FieldReader<PE11_SELECT_A>;
496#[doc = "PE11 Select\n\nValue on reset: 0"]
497#[derive(Clone, Copy, Debug, PartialEq, Eq)]
498#[repr(u8)]
499pub enum PE11_SELECT_A {
500 #[doc = "0: `0`"]
501 INPUT = 0,
502 #[doc = "2: `10`"]
503 NCSI0_D7 = 2,
504 #[doc = "4: `100`"]
505 I2S0_DOUT3 = 4,
506 #[doc = "6: `110`"]
507 JTAG_CK = 6,
508 #[doc = "8: `1000`"]
509 RGMII_TXD2 = 8,
510 #[doc = "14: `1110`"]
511 PE_EINT11 = 14,
512 #[doc = "1: `1`"]
513 OUTPUT = 1,
514 #[doc = "3: `11`"]
515 UART1_RX = 3,
516 #[doc = "5: `101`"]
517 I2S0_DIN3 = 5,
518 #[doc = "15: `1111`"]
519 IO_DISABLE = 15,
520}
521impl From<PE11_SELECT_A> for u8 {
522 #[inline(always)]
523 fn from(variant: PE11_SELECT_A) -> Self {
524 variant as _
525 }
526}
527impl crate::FieldSpec for PE11_SELECT_A {
528 type Ux = u8;
529}
530impl PE11_SELECT_R {
531 #[doc = "Get enumerated values variant"]
532 #[inline(always)]
533 pub const fn variant(&self) -> Option<PE11_SELECT_A> {
534 match self.bits {
535 0 => Some(PE11_SELECT_A::INPUT),
536 2 => Some(PE11_SELECT_A::NCSI0_D7),
537 4 => Some(PE11_SELECT_A::I2S0_DOUT3),
538 6 => Some(PE11_SELECT_A::JTAG_CK),
539 8 => Some(PE11_SELECT_A::RGMII_TXD2),
540 14 => Some(PE11_SELECT_A::PE_EINT11),
541 1 => Some(PE11_SELECT_A::OUTPUT),
542 3 => Some(PE11_SELECT_A::UART1_RX),
543 5 => Some(PE11_SELECT_A::I2S0_DIN3),
544 15 => Some(PE11_SELECT_A::IO_DISABLE),
545 _ => None,
546 }
547 }
548 #[doc = "`0`"]
549 #[inline(always)]
550 pub fn is_input(&self) -> bool {
551 *self == PE11_SELECT_A::INPUT
552 }
553 #[doc = "`10`"]
554 #[inline(always)]
555 pub fn is_ncsi0_d7(&self) -> bool {
556 *self == PE11_SELECT_A::NCSI0_D7
557 }
558 #[doc = "`100`"]
559 #[inline(always)]
560 pub fn is_i2s0_dout3(&self) -> bool {
561 *self == PE11_SELECT_A::I2S0_DOUT3
562 }
563 #[doc = "`110`"]
564 #[inline(always)]
565 pub fn is_jtag_ck(&self) -> bool {
566 *self == PE11_SELECT_A::JTAG_CK
567 }
568 #[doc = "`1000`"]
569 #[inline(always)]
570 pub fn is_rgmii_txd2(&self) -> bool {
571 *self == PE11_SELECT_A::RGMII_TXD2
572 }
573 #[doc = "`1110`"]
574 #[inline(always)]
575 pub fn is_pe_eint11(&self) -> bool {
576 *self == PE11_SELECT_A::PE_EINT11
577 }
578 #[doc = "`1`"]
579 #[inline(always)]
580 pub fn is_output(&self) -> bool {
581 *self == PE11_SELECT_A::OUTPUT
582 }
583 #[doc = "`11`"]
584 #[inline(always)]
585 pub fn is_uart1_rx(&self) -> bool {
586 *self == PE11_SELECT_A::UART1_RX
587 }
588 #[doc = "`101`"]
589 #[inline(always)]
590 pub fn is_i2s0_din3(&self) -> bool {
591 *self == PE11_SELECT_A::I2S0_DIN3
592 }
593 #[doc = "`1111`"]
594 #[inline(always)]
595 pub fn is_io_disable(&self) -> bool {
596 *self == PE11_SELECT_A::IO_DISABLE
597 }
598}
599#[doc = "Field `pe11_select` writer - PE11 Select"]
600pub type PE11_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE11_SELECT_A>;
601impl<'a, REG> PE11_SELECT_W<'a, REG>
602where
603 REG: crate::Writable + crate::RegisterSpec,
604 REG::Ux: From<u8>,
605{
606 #[doc = "`0`"]
607 #[inline(always)]
608 pub fn input(self) -> &'a mut crate::W<REG> {
609 self.variant(PE11_SELECT_A::INPUT)
610 }
611 #[doc = "`10`"]
612 #[inline(always)]
613 pub fn ncsi0_d7(self) -> &'a mut crate::W<REG> {
614 self.variant(PE11_SELECT_A::NCSI0_D7)
615 }
616 #[doc = "`100`"]
617 #[inline(always)]
618 pub fn i2s0_dout3(self) -> &'a mut crate::W<REG> {
619 self.variant(PE11_SELECT_A::I2S0_DOUT3)
620 }
621 #[doc = "`110`"]
622 #[inline(always)]
623 pub fn jtag_ck(self) -> &'a mut crate::W<REG> {
624 self.variant(PE11_SELECT_A::JTAG_CK)
625 }
626 #[doc = "`1000`"]
627 #[inline(always)]
628 pub fn rgmii_txd2(self) -> &'a mut crate::W<REG> {
629 self.variant(PE11_SELECT_A::RGMII_TXD2)
630 }
631 #[doc = "`1110`"]
632 #[inline(always)]
633 pub fn pe_eint11(self) -> &'a mut crate::W<REG> {
634 self.variant(PE11_SELECT_A::PE_EINT11)
635 }
636 #[doc = "`1`"]
637 #[inline(always)]
638 pub fn output(self) -> &'a mut crate::W<REG> {
639 self.variant(PE11_SELECT_A::OUTPUT)
640 }
641 #[doc = "`11`"]
642 #[inline(always)]
643 pub fn uart1_rx(self) -> &'a mut crate::W<REG> {
644 self.variant(PE11_SELECT_A::UART1_RX)
645 }
646 #[doc = "`101`"]
647 #[inline(always)]
648 pub fn i2s0_din3(self) -> &'a mut crate::W<REG> {
649 self.variant(PE11_SELECT_A::I2S0_DIN3)
650 }
651 #[doc = "`1111`"]
652 #[inline(always)]
653 pub fn io_disable(self) -> &'a mut crate::W<REG> {
654 self.variant(PE11_SELECT_A::IO_DISABLE)
655 }
656}
657#[doc = "Field `pe12_select` reader - PE12 Select"]
658pub type PE12_SELECT_R = crate::FieldReader<PE12_SELECT_A>;
659#[doc = "PE12 Select\n\nValue on reset: 0"]
660#[derive(Clone, Copy, Debug, PartialEq, Eq)]
661#[repr(u8)]
662pub enum PE12_SELECT_A {
663 #[doc = "0: `0`"]
664 INPUT = 0,
665 #[doc = "2: `10`"]
666 TWI2_SCK = 2,
667 #[doc = "4: `100`"]
668 I2S0_DOUT2 = 4,
669 #[doc = "8: `1000`"]
670 RGMII_TXD3 = 8,
671 #[doc = "14: `1110`"]
672 PE_EINT12 = 14,
673 #[doc = "1: `1`"]
674 OUTPUT = 1,
675 #[doc = "3: `11`"]
676 NCSI0_FIELD = 3,
677 #[doc = "5: `101`"]
678 I2S0_DIN2 = 5,
679 #[doc = "15: `1111`"]
680 IO_DISABLE = 15,
681}
682impl From<PE12_SELECT_A> for u8 {
683 #[inline(always)]
684 fn from(variant: PE12_SELECT_A) -> Self {
685 variant as _
686 }
687}
688impl crate::FieldSpec for PE12_SELECT_A {
689 type Ux = u8;
690}
691impl PE12_SELECT_R {
692 #[doc = "Get enumerated values variant"]
693 #[inline(always)]
694 pub const fn variant(&self) -> Option<PE12_SELECT_A> {
695 match self.bits {
696 0 => Some(PE12_SELECT_A::INPUT),
697 2 => Some(PE12_SELECT_A::TWI2_SCK),
698 4 => Some(PE12_SELECT_A::I2S0_DOUT2),
699 8 => Some(PE12_SELECT_A::RGMII_TXD3),
700 14 => Some(PE12_SELECT_A::PE_EINT12),
701 1 => Some(PE12_SELECT_A::OUTPUT),
702 3 => Some(PE12_SELECT_A::NCSI0_FIELD),
703 5 => Some(PE12_SELECT_A::I2S0_DIN2),
704 15 => Some(PE12_SELECT_A::IO_DISABLE),
705 _ => None,
706 }
707 }
708 #[doc = "`0`"]
709 #[inline(always)]
710 pub fn is_input(&self) -> bool {
711 *self == PE12_SELECT_A::INPUT
712 }
713 #[doc = "`10`"]
714 #[inline(always)]
715 pub fn is_twi2_sck(&self) -> bool {
716 *self == PE12_SELECT_A::TWI2_SCK
717 }
718 #[doc = "`100`"]
719 #[inline(always)]
720 pub fn is_i2s0_dout2(&self) -> bool {
721 *self == PE12_SELECT_A::I2S0_DOUT2
722 }
723 #[doc = "`1000`"]
724 #[inline(always)]
725 pub fn is_rgmii_txd3(&self) -> bool {
726 *self == PE12_SELECT_A::RGMII_TXD3
727 }
728 #[doc = "`1110`"]
729 #[inline(always)]
730 pub fn is_pe_eint12(&self) -> bool {
731 *self == PE12_SELECT_A::PE_EINT12
732 }
733 #[doc = "`1`"]
734 #[inline(always)]
735 pub fn is_output(&self) -> bool {
736 *self == PE12_SELECT_A::OUTPUT
737 }
738 #[doc = "`11`"]
739 #[inline(always)]
740 pub fn is_ncsi0_field(&self) -> bool {
741 *self == PE12_SELECT_A::NCSI0_FIELD
742 }
743 #[doc = "`101`"]
744 #[inline(always)]
745 pub fn is_i2s0_din2(&self) -> bool {
746 *self == PE12_SELECT_A::I2S0_DIN2
747 }
748 #[doc = "`1111`"]
749 #[inline(always)]
750 pub fn is_io_disable(&self) -> bool {
751 *self == PE12_SELECT_A::IO_DISABLE
752 }
753}
754#[doc = "Field `pe12_select` writer - PE12 Select"]
755pub type PE12_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE12_SELECT_A>;
756impl<'a, REG> PE12_SELECT_W<'a, REG>
757where
758 REG: crate::Writable + crate::RegisterSpec,
759 REG::Ux: From<u8>,
760{
761 #[doc = "`0`"]
762 #[inline(always)]
763 pub fn input(self) -> &'a mut crate::W<REG> {
764 self.variant(PE12_SELECT_A::INPUT)
765 }
766 #[doc = "`10`"]
767 #[inline(always)]
768 pub fn twi2_sck(self) -> &'a mut crate::W<REG> {
769 self.variant(PE12_SELECT_A::TWI2_SCK)
770 }
771 #[doc = "`100`"]
772 #[inline(always)]
773 pub fn i2s0_dout2(self) -> &'a mut crate::W<REG> {
774 self.variant(PE12_SELECT_A::I2S0_DOUT2)
775 }
776 #[doc = "`1000`"]
777 #[inline(always)]
778 pub fn rgmii_txd3(self) -> &'a mut crate::W<REG> {
779 self.variant(PE12_SELECT_A::RGMII_TXD3)
780 }
781 #[doc = "`1110`"]
782 #[inline(always)]
783 pub fn pe_eint12(self) -> &'a mut crate::W<REG> {
784 self.variant(PE12_SELECT_A::PE_EINT12)
785 }
786 #[doc = "`1`"]
787 #[inline(always)]
788 pub fn output(self) -> &'a mut crate::W<REG> {
789 self.variant(PE12_SELECT_A::OUTPUT)
790 }
791 #[doc = "`11`"]
792 #[inline(always)]
793 pub fn ncsi0_field(self) -> &'a mut crate::W<REG> {
794 self.variant(PE12_SELECT_A::NCSI0_FIELD)
795 }
796 #[doc = "`101`"]
797 #[inline(always)]
798 pub fn i2s0_din2(self) -> &'a mut crate::W<REG> {
799 self.variant(PE12_SELECT_A::I2S0_DIN2)
800 }
801 #[doc = "`1111`"]
802 #[inline(always)]
803 pub fn io_disable(self) -> &'a mut crate::W<REG> {
804 self.variant(PE12_SELECT_A::IO_DISABLE)
805 }
806}
807#[doc = "Field `pe13_select` reader - PE13 Select"]
808pub type PE13_SELECT_R = crate::FieldReader<PE13_SELECT_A>;
809#[doc = "PE13 Select\n\nValue on reset: 0"]
810#[derive(Clone, Copy, Debug, PartialEq, Eq)]
811#[repr(u8)]
812pub enum PE13_SELECT_A {
813 #[doc = "0: `0`"]
814 INPUT = 0,
815 #[doc = "2: `10`"]
816 TWI2_SDA = 2,
817 #[doc = "4: `100`"]
818 I2S0_DOUT0 = 4,
819 #[doc = "6: `110`"]
820 DMIC_DATA3 = 6,
821 #[doc = "8: `1000`"]
822 RGMII_RXD2 = 8,
823 #[doc = "14: `1110`"]
824 PE_EINT13 = 14,
825 #[doc = "1: `1`"]
826 OUTPUT = 1,
827 #[doc = "3: `11`"]
828 PWM5 = 3,
829 #[doc = "5: `101`"]
830 I2S0_DIN1 = 5,
831 #[doc = "15: `1111`"]
832 IO_DISABLE = 15,
833}
834impl From<PE13_SELECT_A> for u8 {
835 #[inline(always)]
836 fn from(variant: PE13_SELECT_A) -> Self {
837 variant as _
838 }
839}
840impl crate::FieldSpec for PE13_SELECT_A {
841 type Ux = u8;
842}
843impl PE13_SELECT_R {
844 #[doc = "Get enumerated values variant"]
845 #[inline(always)]
846 pub const fn variant(&self) -> Option<PE13_SELECT_A> {
847 match self.bits {
848 0 => Some(PE13_SELECT_A::INPUT),
849 2 => Some(PE13_SELECT_A::TWI2_SDA),
850 4 => Some(PE13_SELECT_A::I2S0_DOUT0),
851 6 => Some(PE13_SELECT_A::DMIC_DATA3),
852 8 => Some(PE13_SELECT_A::RGMII_RXD2),
853 14 => Some(PE13_SELECT_A::PE_EINT13),
854 1 => Some(PE13_SELECT_A::OUTPUT),
855 3 => Some(PE13_SELECT_A::PWM5),
856 5 => Some(PE13_SELECT_A::I2S0_DIN1),
857 15 => Some(PE13_SELECT_A::IO_DISABLE),
858 _ => None,
859 }
860 }
861 #[doc = "`0`"]
862 #[inline(always)]
863 pub fn is_input(&self) -> bool {
864 *self == PE13_SELECT_A::INPUT
865 }
866 #[doc = "`10`"]
867 #[inline(always)]
868 pub fn is_twi2_sda(&self) -> bool {
869 *self == PE13_SELECT_A::TWI2_SDA
870 }
871 #[doc = "`100`"]
872 #[inline(always)]
873 pub fn is_i2s0_dout0(&self) -> bool {
874 *self == PE13_SELECT_A::I2S0_DOUT0
875 }
876 #[doc = "`110`"]
877 #[inline(always)]
878 pub fn is_dmic_data3(&self) -> bool {
879 *self == PE13_SELECT_A::DMIC_DATA3
880 }
881 #[doc = "`1000`"]
882 #[inline(always)]
883 pub fn is_rgmii_rxd2(&self) -> bool {
884 *self == PE13_SELECT_A::RGMII_RXD2
885 }
886 #[doc = "`1110`"]
887 #[inline(always)]
888 pub fn is_pe_eint13(&self) -> bool {
889 *self == PE13_SELECT_A::PE_EINT13
890 }
891 #[doc = "`1`"]
892 #[inline(always)]
893 pub fn is_output(&self) -> bool {
894 *self == PE13_SELECT_A::OUTPUT
895 }
896 #[doc = "`11`"]
897 #[inline(always)]
898 pub fn is_pwm5(&self) -> bool {
899 *self == PE13_SELECT_A::PWM5
900 }
901 #[doc = "`101`"]
902 #[inline(always)]
903 pub fn is_i2s0_din1(&self) -> bool {
904 *self == PE13_SELECT_A::I2S0_DIN1
905 }
906 #[doc = "`1111`"]
907 #[inline(always)]
908 pub fn is_io_disable(&self) -> bool {
909 *self == PE13_SELECT_A::IO_DISABLE
910 }
911}
912#[doc = "Field `pe13_select` writer - PE13 Select"]
913pub type PE13_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE13_SELECT_A>;
914impl<'a, REG> PE13_SELECT_W<'a, REG>
915where
916 REG: crate::Writable + crate::RegisterSpec,
917 REG::Ux: From<u8>,
918{
919 #[doc = "`0`"]
920 #[inline(always)]
921 pub fn input(self) -> &'a mut crate::W<REG> {
922 self.variant(PE13_SELECT_A::INPUT)
923 }
924 #[doc = "`10`"]
925 #[inline(always)]
926 pub fn twi2_sda(self) -> &'a mut crate::W<REG> {
927 self.variant(PE13_SELECT_A::TWI2_SDA)
928 }
929 #[doc = "`100`"]
930 #[inline(always)]
931 pub fn i2s0_dout0(self) -> &'a mut crate::W<REG> {
932 self.variant(PE13_SELECT_A::I2S0_DOUT0)
933 }
934 #[doc = "`110`"]
935 #[inline(always)]
936 pub fn dmic_data3(self) -> &'a mut crate::W<REG> {
937 self.variant(PE13_SELECT_A::DMIC_DATA3)
938 }
939 #[doc = "`1000`"]
940 #[inline(always)]
941 pub fn rgmii_rxd2(self) -> &'a mut crate::W<REG> {
942 self.variant(PE13_SELECT_A::RGMII_RXD2)
943 }
944 #[doc = "`1110`"]
945 #[inline(always)]
946 pub fn pe_eint13(self) -> &'a mut crate::W<REG> {
947 self.variant(PE13_SELECT_A::PE_EINT13)
948 }
949 #[doc = "`1`"]
950 #[inline(always)]
951 pub fn output(self) -> &'a mut crate::W<REG> {
952 self.variant(PE13_SELECT_A::OUTPUT)
953 }
954 #[doc = "`11`"]
955 #[inline(always)]
956 pub fn pwm5(self) -> &'a mut crate::W<REG> {
957 self.variant(PE13_SELECT_A::PWM5)
958 }
959 #[doc = "`101`"]
960 #[inline(always)]
961 pub fn i2s0_din1(self) -> &'a mut crate::W<REG> {
962 self.variant(PE13_SELECT_A::I2S0_DIN1)
963 }
964 #[doc = "`1111`"]
965 #[inline(always)]
966 pub fn io_disable(self) -> &'a mut crate::W<REG> {
967 self.variant(PE13_SELECT_A::IO_DISABLE)
968 }
969}
970#[doc = "Field `pe14_select` reader - PE14 Select"]
971pub type PE14_SELECT_R = crate::FieldReader<PE14_SELECT_A>;
972#[doc = "PE14 Select\n\nValue on reset: 0"]
973#[derive(Clone, Copy, Debug, PartialEq, Eq)]
974#[repr(u8)]
975pub enum PE14_SELECT_A {
976 #[doc = "0: `0`"]
977 INPUT = 0,
978 #[doc = "2: `10`"]
979 TWI1_SCK = 2,
980 #[doc = "4: `100`"]
981 I2S0_DOUT1 = 4,
982 #[doc = "6: `110`"]
983 DMIC_DATA2 = 6,
984 #[doc = "8: `1000`"]
985 RGMII_RXD3 = 8,
986 #[doc = "14: `1110`"]
987 PE_EINT14 = 14,
988 #[doc = "1: `1`"]
989 OUTPUT = 1,
990 #[doc = "3: `11`"]
991 D_JTAG_MS = 3,
992 #[doc = "5: `101`"]
993 I2S0_DIN0 = 5,
994 #[doc = "15: `1111`"]
995 IO_DISABLE = 15,
996}
997impl From<PE14_SELECT_A> for u8 {
998 #[inline(always)]
999 fn from(variant: PE14_SELECT_A) -> Self {
1000 variant as _
1001 }
1002}
1003impl crate::FieldSpec for PE14_SELECT_A {
1004 type Ux = u8;
1005}
1006impl PE14_SELECT_R {
1007 #[doc = "Get enumerated values variant"]
1008 #[inline(always)]
1009 pub const fn variant(&self) -> Option<PE14_SELECT_A> {
1010 match self.bits {
1011 0 => Some(PE14_SELECT_A::INPUT),
1012 2 => Some(PE14_SELECT_A::TWI1_SCK),
1013 4 => Some(PE14_SELECT_A::I2S0_DOUT1),
1014 6 => Some(PE14_SELECT_A::DMIC_DATA2),
1015 8 => Some(PE14_SELECT_A::RGMII_RXD3),
1016 14 => Some(PE14_SELECT_A::PE_EINT14),
1017 1 => Some(PE14_SELECT_A::OUTPUT),
1018 3 => Some(PE14_SELECT_A::D_JTAG_MS),
1019 5 => Some(PE14_SELECT_A::I2S0_DIN0),
1020 15 => Some(PE14_SELECT_A::IO_DISABLE),
1021 _ => None,
1022 }
1023 }
1024 #[doc = "`0`"]
1025 #[inline(always)]
1026 pub fn is_input(&self) -> bool {
1027 *self == PE14_SELECT_A::INPUT
1028 }
1029 #[doc = "`10`"]
1030 #[inline(always)]
1031 pub fn is_twi1_sck(&self) -> bool {
1032 *self == PE14_SELECT_A::TWI1_SCK
1033 }
1034 #[doc = "`100`"]
1035 #[inline(always)]
1036 pub fn is_i2s0_dout1(&self) -> bool {
1037 *self == PE14_SELECT_A::I2S0_DOUT1
1038 }
1039 #[doc = "`110`"]
1040 #[inline(always)]
1041 pub fn is_dmic_data2(&self) -> bool {
1042 *self == PE14_SELECT_A::DMIC_DATA2
1043 }
1044 #[doc = "`1000`"]
1045 #[inline(always)]
1046 pub fn is_rgmii_rxd3(&self) -> bool {
1047 *self == PE14_SELECT_A::RGMII_RXD3
1048 }
1049 #[doc = "`1110`"]
1050 #[inline(always)]
1051 pub fn is_pe_eint14(&self) -> bool {
1052 *self == PE14_SELECT_A::PE_EINT14
1053 }
1054 #[doc = "`1`"]
1055 #[inline(always)]
1056 pub fn is_output(&self) -> bool {
1057 *self == PE14_SELECT_A::OUTPUT
1058 }
1059 #[doc = "`11`"]
1060 #[inline(always)]
1061 pub fn is_d_jtag_ms(&self) -> bool {
1062 *self == PE14_SELECT_A::D_JTAG_MS
1063 }
1064 #[doc = "`101`"]
1065 #[inline(always)]
1066 pub fn is_i2s0_din0(&self) -> bool {
1067 *self == PE14_SELECT_A::I2S0_DIN0
1068 }
1069 #[doc = "`1111`"]
1070 #[inline(always)]
1071 pub fn is_io_disable(&self) -> bool {
1072 *self == PE14_SELECT_A::IO_DISABLE
1073 }
1074}
1075#[doc = "Field `pe14_select` writer - PE14 Select"]
1076pub type PE14_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE14_SELECT_A>;
1077impl<'a, REG> PE14_SELECT_W<'a, REG>
1078where
1079 REG: crate::Writable + crate::RegisterSpec,
1080 REG::Ux: From<u8>,
1081{
1082 #[doc = "`0`"]
1083 #[inline(always)]
1084 pub fn input(self) -> &'a mut crate::W<REG> {
1085 self.variant(PE14_SELECT_A::INPUT)
1086 }
1087 #[doc = "`10`"]
1088 #[inline(always)]
1089 pub fn twi1_sck(self) -> &'a mut crate::W<REG> {
1090 self.variant(PE14_SELECT_A::TWI1_SCK)
1091 }
1092 #[doc = "`100`"]
1093 #[inline(always)]
1094 pub fn i2s0_dout1(self) -> &'a mut crate::W<REG> {
1095 self.variant(PE14_SELECT_A::I2S0_DOUT1)
1096 }
1097 #[doc = "`110`"]
1098 #[inline(always)]
1099 pub fn dmic_data2(self) -> &'a mut crate::W<REG> {
1100 self.variant(PE14_SELECT_A::DMIC_DATA2)
1101 }
1102 #[doc = "`1000`"]
1103 #[inline(always)]
1104 pub fn rgmii_rxd3(self) -> &'a mut crate::W<REG> {
1105 self.variant(PE14_SELECT_A::RGMII_RXD3)
1106 }
1107 #[doc = "`1110`"]
1108 #[inline(always)]
1109 pub fn pe_eint14(self) -> &'a mut crate::W<REG> {
1110 self.variant(PE14_SELECT_A::PE_EINT14)
1111 }
1112 #[doc = "`1`"]
1113 #[inline(always)]
1114 pub fn output(self) -> &'a mut crate::W<REG> {
1115 self.variant(PE14_SELECT_A::OUTPUT)
1116 }
1117 #[doc = "`11`"]
1118 #[inline(always)]
1119 pub fn d_jtag_ms(self) -> &'a mut crate::W<REG> {
1120 self.variant(PE14_SELECT_A::D_JTAG_MS)
1121 }
1122 #[doc = "`101`"]
1123 #[inline(always)]
1124 pub fn i2s0_din0(self) -> &'a mut crate::W<REG> {
1125 self.variant(PE14_SELECT_A::I2S0_DIN0)
1126 }
1127 #[doc = "`1111`"]
1128 #[inline(always)]
1129 pub fn io_disable(self) -> &'a mut crate::W<REG> {
1130 self.variant(PE14_SELECT_A::IO_DISABLE)
1131 }
1132}
1133#[doc = "Field `pe15_select` reader - PE15 Select"]
1134pub type PE15_SELECT_R = crate::FieldReader<PE15_SELECT_A>;
1135#[doc = "PE15 Select\n\nValue on reset: 0"]
1136#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1137#[repr(u8)]
1138pub enum PE15_SELECT_A {
1139 #[doc = "0: `0`"]
1140 INPUT = 0,
1141 #[doc = "2: `10`"]
1142 TWI1_SDA = 2,
1143 #[doc = "4: `100`"]
1144 PWM6 = 4,
1145 #[doc = "6: `110`"]
1146 DMIC_DATA1 = 6,
1147 #[doc = "8: `1000`"]
1148 RGMII_RXCK = 8,
1149 #[doc = "14: `1110`"]
1150 PE_EINT15 = 14,
1151 #[doc = "1: `1`"]
1152 OUTPUT = 1,
1153 #[doc = "3: `11`"]
1154 D_JTAG_DI = 3,
1155 #[doc = "5: `101`"]
1156 I2S0_LRCK = 5,
1157 #[doc = "15: `1111`"]
1158 IO_DISABLE = 15,
1159}
1160impl From<PE15_SELECT_A> for u8 {
1161 #[inline(always)]
1162 fn from(variant: PE15_SELECT_A) -> Self {
1163 variant as _
1164 }
1165}
1166impl crate::FieldSpec for PE15_SELECT_A {
1167 type Ux = u8;
1168}
1169impl PE15_SELECT_R {
1170 #[doc = "Get enumerated values variant"]
1171 #[inline(always)]
1172 pub const fn variant(&self) -> Option<PE15_SELECT_A> {
1173 match self.bits {
1174 0 => Some(PE15_SELECT_A::INPUT),
1175 2 => Some(PE15_SELECT_A::TWI1_SDA),
1176 4 => Some(PE15_SELECT_A::PWM6),
1177 6 => Some(PE15_SELECT_A::DMIC_DATA1),
1178 8 => Some(PE15_SELECT_A::RGMII_RXCK),
1179 14 => Some(PE15_SELECT_A::PE_EINT15),
1180 1 => Some(PE15_SELECT_A::OUTPUT),
1181 3 => Some(PE15_SELECT_A::D_JTAG_DI),
1182 5 => Some(PE15_SELECT_A::I2S0_LRCK),
1183 15 => Some(PE15_SELECT_A::IO_DISABLE),
1184 _ => None,
1185 }
1186 }
1187 #[doc = "`0`"]
1188 #[inline(always)]
1189 pub fn is_input(&self) -> bool {
1190 *self == PE15_SELECT_A::INPUT
1191 }
1192 #[doc = "`10`"]
1193 #[inline(always)]
1194 pub fn is_twi1_sda(&self) -> bool {
1195 *self == PE15_SELECT_A::TWI1_SDA
1196 }
1197 #[doc = "`100`"]
1198 #[inline(always)]
1199 pub fn is_pwm6(&self) -> bool {
1200 *self == PE15_SELECT_A::PWM6
1201 }
1202 #[doc = "`110`"]
1203 #[inline(always)]
1204 pub fn is_dmic_data1(&self) -> bool {
1205 *self == PE15_SELECT_A::DMIC_DATA1
1206 }
1207 #[doc = "`1000`"]
1208 #[inline(always)]
1209 pub fn is_rgmii_rxck(&self) -> bool {
1210 *self == PE15_SELECT_A::RGMII_RXCK
1211 }
1212 #[doc = "`1110`"]
1213 #[inline(always)]
1214 pub fn is_pe_eint15(&self) -> bool {
1215 *self == PE15_SELECT_A::PE_EINT15
1216 }
1217 #[doc = "`1`"]
1218 #[inline(always)]
1219 pub fn is_output(&self) -> bool {
1220 *self == PE15_SELECT_A::OUTPUT
1221 }
1222 #[doc = "`11`"]
1223 #[inline(always)]
1224 pub fn is_d_jtag_di(&self) -> bool {
1225 *self == PE15_SELECT_A::D_JTAG_DI
1226 }
1227 #[doc = "`101`"]
1228 #[inline(always)]
1229 pub fn is_i2s0_lrck(&self) -> bool {
1230 *self == PE15_SELECT_A::I2S0_LRCK
1231 }
1232 #[doc = "`1111`"]
1233 #[inline(always)]
1234 pub fn is_io_disable(&self) -> bool {
1235 *self == PE15_SELECT_A::IO_DISABLE
1236 }
1237}
1238#[doc = "Field `pe15_select` writer - PE15 Select"]
1239pub type PE15_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE15_SELECT_A>;
1240impl<'a, REG> PE15_SELECT_W<'a, REG>
1241where
1242 REG: crate::Writable + crate::RegisterSpec,
1243 REG::Ux: From<u8>,
1244{
1245 #[doc = "`0`"]
1246 #[inline(always)]
1247 pub fn input(self) -> &'a mut crate::W<REG> {
1248 self.variant(PE15_SELECT_A::INPUT)
1249 }
1250 #[doc = "`10`"]
1251 #[inline(always)]
1252 pub fn twi1_sda(self) -> &'a mut crate::W<REG> {
1253 self.variant(PE15_SELECT_A::TWI1_SDA)
1254 }
1255 #[doc = "`100`"]
1256 #[inline(always)]
1257 pub fn pwm6(self) -> &'a mut crate::W<REG> {
1258 self.variant(PE15_SELECT_A::PWM6)
1259 }
1260 #[doc = "`110`"]
1261 #[inline(always)]
1262 pub fn dmic_data1(self) -> &'a mut crate::W<REG> {
1263 self.variant(PE15_SELECT_A::DMIC_DATA1)
1264 }
1265 #[doc = "`1000`"]
1266 #[inline(always)]
1267 pub fn rgmii_rxck(self) -> &'a mut crate::W<REG> {
1268 self.variant(PE15_SELECT_A::RGMII_RXCK)
1269 }
1270 #[doc = "`1110`"]
1271 #[inline(always)]
1272 pub fn pe_eint15(self) -> &'a mut crate::W<REG> {
1273 self.variant(PE15_SELECT_A::PE_EINT15)
1274 }
1275 #[doc = "`1`"]
1276 #[inline(always)]
1277 pub fn output(self) -> &'a mut crate::W<REG> {
1278 self.variant(PE15_SELECT_A::OUTPUT)
1279 }
1280 #[doc = "`11`"]
1281 #[inline(always)]
1282 pub fn d_jtag_di(self) -> &'a mut crate::W<REG> {
1283 self.variant(PE15_SELECT_A::D_JTAG_DI)
1284 }
1285 #[doc = "`101`"]
1286 #[inline(always)]
1287 pub fn i2s0_lrck(self) -> &'a mut crate::W<REG> {
1288 self.variant(PE15_SELECT_A::I2S0_LRCK)
1289 }
1290 #[doc = "`1111`"]
1291 #[inline(always)]
1292 pub fn io_disable(self) -> &'a mut crate::W<REG> {
1293 self.variant(PE15_SELECT_A::IO_DISABLE)
1294 }
1295}
1296impl R {
1297 #[doc = "Bits 0:3 - PE8 Select"]
1298 #[inline(always)]
1299 pub fn pe8_select(&self) -> PE8_SELECT_R {
1300 PE8_SELECT_R::new((self.bits & 0x0f) as u8)
1301 }
1302 #[doc = "Bits 4:7 - PE9 Select"]
1303 #[inline(always)]
1304 pub fn pe9_select(&self) -> PE9_SELECT_R {
1305 PE9_SELECT_R::new(((self.bits >> 4) & 0x0f) as u8)
1306 }
1307 #[doc = "Bits 8:11 - PE10 Select"]
1308 #[inline(always)]
1309 pub fn pe10_select(&self) -> PE10_SELECT_R {
1310 PE10_SELECT_R::new(((self.bits >> 8) & 0x0f) as u8)
1311 }
1312 #[doc = "Bits 12:15 - PE11 Select"]
1313 #[inline(always)]
1314 pub fn pe11_select(&self) -> PE11_SELECT_R {
1315 PE11_SELECT_R::new(((self.bits >> 12) & 0x0f) as u8)
1316 }
1317 #[doc = "Bits 16:19 - PE12 Select"]
1318 #[inline(always)]
1319 pub fn pe12_select(&self) -> PE12_SELECT_R {
1320 PE12_SELECT_R::new(((self.bits >> 16) & 0x0f) as u8)
1321 }
1322 #[doc = "Bits 20:23 - PE13 Select"]
1323 #[inline(always)]
1324 pub fn pe13_select(&self) -> PE13_SELECT_R {
1325 PE13_SELECT_R::new(((self.bits >> 20) & 0x0f) as u8)
1326 }
1327 #[doc = "Bits 24:27 - PE14 Select"]
1328 #[inline(always)]
1329 pub fn pe14_select(&self) -> PE14_SELECT_R {
1330 PE14_SELECT_R::new(((self.bits >> 24) & 0x0f) as u8)
1331 }
1332 #[doc = "Bits 28:31 - PE15 Select"]
1333 #[inline(always)]
1334 pub fn pe15_select(&self) -> PE15_SELECT_R {
1335 PE15_SELECT_R::new(((self.bits >> 28) & 0x0f) as u8)
1336 }
1337}
1338impl W {
1339 #[doc = "Bits 0:3 - PE8 Select"]
1340 #[inline(always)]
1341 #[must_use]
1342 pub fn pe8_select(&mut self) -> PE8_SELECT_W<PE_CFG1_SPEC> {
1343 PE8_SELECT_W::new(self, 0)
1344 }
1345 #[doc = "Bits 4:7 - PE9 Select"]
1346 #[inline(always)]
1347 #[must_use]
1348 pub fn pe9_select(&mut self) -> PE9_SELECT_W<PE_CFG1_SPEC> {
1349 PE9_SELECT_W::new(self, 4)
1350 }
1351 #[doc = "Bits 8:11 - PE10 Select"]
1352 #[inline(always)]
1353 #[must_use]
1354 pub fn pe10_select(&mut self) -> PE10_SELECT_W<PE_CFG1_SPEC> {
1355 PE10_SELECT_W::new(self, 8)
1356 }
1357 #[doc = "Bits 12:15 - PE11 Select"]
1358 #[inline(always)]
1359 #[must_use]
1360 pub fn pe11_select(&mut self) -> PE11_SELECT_W<PE_CFG1_SPEC> {
1361 PE11_SELECT_W::new(self, 12)
1362 }
1363 #[doc = "Bits 16:19 - PE12 Select"]
1364 #[inline(always)]
1365 #[must_use]
1366 pub fn pe12_select(&mut self) -> PE12_SELECT_W<PE_CFG1_SPEC> {
1367 PE12_SELECT_W::new(self, 16)
1368 }
1369 #[doc = "Bits 20:23 - PE13 Select"]
1370 #[inline(always)]
1371 #[must_use]
1372 pub fn pe13_select(&mut self) -> PE13_SELECT_W<PE_CFG1_SPEC> {
1373 PE13_SELECT_W::new(self, 20)
1374 }
1375 #[doc = "Bits 24:27 - PE14 Select"]
1376 #[inline(always)]
1377 #[must_use]
1378 pub fn pe14_select(&mut self) -> PE14_SELECT_W<PE_CFG1_SPEC> {
1379 PE14_SELECT_W::new(self, 24)
1380 }
1381 #[doc = "Bits 28:31 - PE15 Select"]
1382 #[inline(always)]
1383 #[must_use]
1384 pub fn pe15_select(&mut self) -> PE15_SELECT_W<PE_CFG1_SPEC> {
1385 PE15_SELECT_W::new(self, 28)
1386 }
1387 #[doc = r" Writes raw bits to the register."]
1388 #[doc = r""]
1389 #[doc = r" # Safety"]
1390 #[doc = r""]
1391 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
1392 #[inline(always)]
1393 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1394 self.bits = bits;
1395 self
1396 }
1397}
1398#[doc = "PE Configure Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pe_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pe_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1399pub struct PE_CFG1_SPEC;
1400impl crate::RegisterSpec for PE_CFG1_SPEC {
1401 type Ux = u32;
1402}
1403#[doc = "`read()` method returns [`pe_cfg1::R`](R) reader structure"]
1404impl crate::Readable for PE_CFG1_SPEC {}
1405#[doc = "`write(|w| ..)` method takes [`pe_cfg1::W`](W) writer structure"]
1406impl crate::Writable for PE_CFG1_SPEC {
1407 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1408 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1409}
1410#[doc = "`reset()` method sets pe_cfg1 to value 0"]
1411impl crate::Resettable for PE_CFG1_SPEC {
1412 const RESET_VALUE: Self::Ux = 0;
1413}