d1_pac/gpio/
pd_eint_cfg2.rs

1#[doc = "Register `pd_eint_cfg2` reader"]
2pub type R = crate::R<PD_EINT_CFG2_SPEC>;
3#[doc = "Register `pd_eint_cfg2` writer"]
4pub type W = crate::W<PD_EINT_CFG2_SPEC>;
5#[doc = "Field `eint_cfg[16-22]` reader - External INT Mode"]
6pub type EINT_CFG_R = crate::FieldReader<EINT_CFG_A>;
7#[doc = "External INT Mode\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum EINT_CFG_A {
11    #[doc = "0: `0`"]
12    POSITIVE_EDGE = 0,
13    #[doc = "1: `1`"]
14    NEGATIVE_EDGE = 1,
15    #[doc = "2: `10`"]
16    HIGH_LEVEL = 2,
17    #[doc = "3: `11`"]
18    LOW_LEVEL = 3,
19    #[doc = "4: `100`"]
20    DOUBLE_EDGE = 4,
21}
22impl From<EINT_CFG_A> for u8 {
23    #[inline(always)]
24    fn from(variant: EINT_CFG_A) -> Self {
25        variant as _
26    }
27}
28impl crate::FieldSpec for EINT_CFG_A {
29    type Ux = u8;
30}
31impl EINT_CFG_R {
32    #[doc = "Get enumerated values variant"]
33    #[inline(always)]
34    pub const fn variant(&self) -> Option<EINT_CFG_A> {
35        match self.bits {
36            0 => Some(EINT_CFG_A::POSITIVE_EDGE),
37            1 => Some(EINT_CFG_A::NEGATIVE_EDGE),
38            2 => Some(EINT_CFG_A::HIGH_LEVEL),
39            3 => Some(EINT_CFG_A::LOW_LEVEL),
40            4 => Some(EINT_CFG_A::DOUBLE_EDGE),
41            _ => None,
42        }
43    }
44    #[doc = "`0`"]
45    #[inline(always)]
46    pub fn is_positive_edge(&self) -> bool {
47        *self == EINT_CFG_A::POSITIVE_EDGE
48    }
49    #[doc = "`1`"]
50    #[inline(always)]
51    pub fn is_negative_edge(&self) -> bool {
52        *self == EINT_CFG_A::NEGATIVE_EDGE
53    }
54    #[doc = "`10`"]
55    #[inline(always)]
56    pub fn is_high_level(&self) -> bool {
57        *self == EINT_CFG_A::HIGH_LEVEL
58    }
59    #[doc = "`11`"]
60    #[inline(always)]
61    pub fn is_low_level(&self) -> bool {
62        *self == EINT_CFG_A::LOW_LEVEL
63    }
64    #[doc = "`100`"]
65    #[inline(always)]
66    pub fn is_double_edge(&self) -> bool {
67        *self == EINT_CFG_A::DOUBLE_EDGE
68    }
69}
70#[doc = "Field `eint_cfg[16-22]` writer - External INT Mode"]
71pub type EINT_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 4, EINT_CFG_A>;
72impl<'a, REG> EINT_CFG_W<'a, REG>
73where
74    REG: crate::Writable + crate::RegisterSpec,
75    REG::Ux: From<u8>,
76{
77    #[doc = "`0`"]
78    #[inline(always)]
79    pub fn positive_edge(self) -> &'a mut crate::W<REG> {
80        self.variant(EINT_CFG_A::POSITIVE_EDGE)
81    }
82    #[doc = "`1`"]
83    #[inline(always)]
84    pub fn negative_edge(self) -> &'a mut crate::W<REG> {
85        self.variant(EINT_CFG_A::NEGATIVE_EDGE)
86    }
87    #[doc = "`10`"]
88    #[inline(always)]
89    pub fn high_level(self) -> &'a mut crate::W<REG> {
90        self.variant(EINT_CFG_A::HIGH_LEVEL)
91    }
92    #[doc = "`11`"]
93    #[inline(always)]
94    pub fn low_level(self) -> &'a mut crate::W<REG> {
95        self.variant(EINT_CFG_A::LOW_LEVEL)
96    }
97    #[doc = "`100`"]
98    #[inline(always)]
99    pub fn double_edge(self) -> &'a mut crate::W<REG> {
100        self.variant(EINT_CFG_A::DOUBLE_EDGE)
101    }
102}
103impl R {
104    #[doc = "External INT Mode\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `eint16_cfg` field"]
105    #[inline(always)]
106    pub fn eint_cfg(&self, n: u8) -> EINT_CFG_R {
107        #[allow(clippy::no_effect)]
108        [(); 7][n as usize];
109        EINT_CFG_R::new(((self.bits >> (n * 4)) & 0x0f) as u8)
110    }
111    #[doc = "Bits 0:3 - External INT Mode"]
112    #[inline(always)]
113    pub fn eint16_cfg(&self) -> EINT_CFG_R {
114        EINT_CFG_R::new((self.bits & 0x0f) as u8)
115    }
116    #[doc = "Bits 4:7 - External INT Mode"]
117    #[inline(always)]
118    pub fn eint17_cfg(&self) -> EINT_CFG_R {
119        EINT_CFG_R::new(((self.bits >> 4) & 0x0f) as u8)
120    }
121    #[doc = "Bits 8:11 - External INT Mode"]
122    #[inline(always)]
123    pub fn eint18_cfg(&self) -> EINT_CFG_R {
124        EINT_CFG_R::new(((self.bits >> 8) & 0x0f) as u8)
125    }
126    #[doc = "Bits 12:15 - External INT Mode"]
127    #[inline(always)]
128    pub fn eint19_cfg(&self) -> EINT_CFG_R {
129        EINT_CFG_R::new(((self.bits >> 12) & 0x0f) as u8)
130    }
131    #[doc = "Bits 16:19 - External INT Mode"]
132    #[inline(always)]
133    pub fn eint20_cfg(&self) -> EINT_CFG_R {
134        EINT_CFG_R::new(((self.bits >> 16) & 0x0f) as u8)
135    }
136    #[doc = "Bits 20:23 - External INT Mode"]
137    #[inline(always)]
138    pub fn eint21_cfg(&self) -> EINT_CFG_R {
139        EINT_CFG_R::new(((self.bits >> 20) & 0x0f) as u8)
140    }
141    #[doc = "Bits 24:27 - External INT Mode"]
142    #[inline(always)]
143    pub fn eint22_cfg(&self) -> EINT_CFG_R {
144        EINT_CFG_R::new(((self.bits >> 24) & 0x0f) as u8)
145    }
146}
147impl W {
148    #[doc = "External INT Mode\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `eint16_cfg` field"]
149    #[inline(always)]
150    #[must_use]
151    pub fn eint_cfg(&mut self, n: u8) -> EINT_CFG_W<PD_EINT_CFG2_SPEC> {
152        #[allow(clippy::no_effect)]
153        [(); 7][n as usize];
154        EINT_CFG_W::new(self, n * 4)
155    }
156    #[doc = "Bits 0:3 - External INT Mode"]
157    #[inline(always)]
158    #[must_use]
159    pub fn eint16_cfg(&mut self) -> EINT_CFG_W<PD_EINT_CFG2_SPEC> {
160        EINT_CFG_W::new(self, 0)
161    }
162    #[doc = "Bits 4:7 - External INT Mode"]
163    #[inline(always)]
164    #[must_use]
165    pub fn eint17_cfg(&mut self) -> EINT_CFG_W<PD_EINT_CFG2_SPEC> {
166        EINT_CFG_W::new(self, 4)
167    }
168    #[doc = "Bits 8:11 - External INT Mode"]
169    #[inline(always)]
170    #[must_use]
171    pub fn eint18_cfg(&mut self) -> EINT_CFG_W<PD_EINT_CFG2_SPEC> {
172        EINT_CFG_W::new(self, 8)
173    }
174    #[doc = "Bits 12:15 - External INT Mode"]
175    #[inline(always)]
176    #[must_use]
177    pub fn eint19_cfg(&mut self) -> EINT_CFG_W<PD_EINT_CFG2_SPEC> {
178        EINT_CFG_W::new(self, 12)
179    }
180    #[doc = "Bits 16:19 - External INT Mode"]
181    #[inline(always)]
182    #[must_use]
183    pub fn eint20_cfg(&mut self) -> EINT_CFG_W<PD_EINT_CFG2_SPEC> {
184        EINT_CFG_W::new(self, 16)
185    }
186    #[doc = "Bits 20:23 - External INT Mode"]
187    #[inline(always)]
188    #[must_use]
189    pub fn eint21_cfg(&mut self) -> EINT_CFG_W<PD_EINT_CFG2_SPEC> {
190        EINT_CFG_W::new(self, 20)
191    }
192    #[doc = "Bits 24:27 - External INT Mode"]
193    #[inline(always)]
194    #[must_use]
195    pub fn eint22_cfg(&mut self) -> EINT_CFG_W<PD_EINT_CFG2_SPEC> {
196        EINT_CFG_W::new(self, 24)
197    }
198    #[doc = r" Writes raw bits to the register."]
199    #[doc = r""]
200    #[doc = r" # Safety"]
201    #[doc = r""]
202    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
203    #[inline(always)]
204    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
205        self.bits = bits;
206        self
207    }
208}
209#[doc = "PD External Interrupt Configure Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pd_eint_cfg2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pd_eint_cfg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
210pub struct PD_EINT_CFG2_SPEC;
211impl crate::RegisterSpec for PD_EINT_CFG2_SPEC {
212    type Ux = u32;
213}
214#[doc = "`read()` method returns [`pd_eint_cfg2::R`](R) reader structure"]
215impl crate::Readable for PD_EINT_CFG2_SPEC {}
216#[doc = "`write(|w| ..)` method takes [`pd_eint_cfg2::W`](W) writer structure"]
217impl crate::Writable for PD_EINT_CFG2_SPEC {
218    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
219    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
220}
221#[doc = "`reset()` method sets pd_eint_cfg2 to value 0"]
222impl crate::Resettable for PD_EINT_CFG2_SPEC {
223    const RESET_VALUE: Self::Ux = 0;
224}
d1_pac/gpio/pd_eint_cfg2.rs

d1_pac/gpio/
pd_eint_cfg2.rs
