d1_pac/gpio/
pd_cfg2.rs

1#[doc = "Register `pd_cfg2` reader"]
2pub type R = crate::R<PD_CFG2_SPEC>;
3#[doc = "Register `pd_cfg2` writer"]
4pub type W = crate::W<PD_CFG2_SPEC>;
5#[doc = "Field `pd16_select` reader - PD16 Select"]
6pub type PD16_SELECT_R = crate::FieldReader<PD16_SELECT_A>;
7#[doc = "PD16 Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum PD16_SELECT_A {
11    #[doc = "0: `0`"]
12    INPUT = 0,
13    #[doc = "2: `10`"]
14    LCD0_D22 = 2,
15    #[doc = "4: `100`"]
16    DMIC_DATA3 = 4,
17    #[doc = "14: `1110`"]
18    PD_EINT16 = 14,
19    #[doc = "1: `1`"]
20    OUTPUT = 1,
21    #[doc = "3: `11`"]
22    LVDS1_CKP = 3,
23    #[doc = "5: `101`"]
24    PWM0 = 5,
25    #[doc = "15: `1111`"]
26    IO_DISABLE = 15,
27}
28impl From<PD16_SELECT_A> for u8 {
29    #[inline(always)]
30    fn from(variant: PD16_SELECT_A) -> Self {
31        variant as _
32    }
33}
34impl crate::FieldSpec for PD16_SELECT_A {
35    type Ux = u8;
36}
37impl PD16_SELECT_R {
38    #[doc = "Get enumerated values variant"]
39    #[inline(always)]
40    pub const fn variant(&self) -> Option<PD16_SELECT_A> {
41        match self.bits {
42            0 => Some(PD16_SELECT_A::INPUT),
43            2 => Some(PD16_SELECT_A::LCD0_D22),
44            4 => Some(PD16_SELECT_A::DMIC_DATA3),
45            14 => Some(PD16_SELECT_A::PD_EINT16),
46            1 => Some(PD16_SELECT_A::OUTPUT),
47            3 => Some(PD16_SELECT_A::LVDS1_CKP),
48            5 => Some(PD16_SELECT_A::PWM0),
49            15 => Some(PD16_SELECT_A::IO_DISABLE),
50            _ => None,
51        }
52    }
53    #[doc = "`0`"]
54    #[inline(always)]
55    pub fn is_input(&self) -> bool {
56        *self == PD16_SELECT_A::INPUT
57    }
58    #[doc = "`10`"]
59    #[inline(always)]
60    pub fn is_lcd0_d22(&self) -> bool {
61        *self == PD16_SELECT_A::LCD0_D22
62    }
63    #[doc = "`100`"]
64    #[inline(always)]
65    pub fn is_dmic_data3(&self) -> bool {
66        *self == PD16_SELECT_A::DMIC_DATA3
67    }
68    #[doc = "`1110`"]
69    #[inline(always)]
70    pub fn is_pd_eint16(&self) -> bool {
71        *self == PD16_SELECT_A::PD_EINT16
72    }
73    #[doc = "`1`"]
74    #[inline(always)]
75    pub fn is_output(&self) -> bool {
76        *self == PD16_SELECT_A::OUTPUT
77    }
78    #[doc = "`11`"]
79    #[inline(always)]
80    pub fn is_lvds1_ckp(&self) -> bool {
81        *self == PD16_SELECT_A::LVDS1_CKP
82    }
83    #[doc = "`101`"]
84    #[inline(always)]
85    pub fn is_pwm0(&self) -> bool {
86        *self == PD16_SELECT_A::PWM0
87    }
88    #[doc = "`1111`"]
89    #[inline(always)]
90    pub fn is_io_disable(&self) -> bool {
91        *self == PD16_SELECT_A::IO_DISABLE
92    }
93}
94#[doc = "Field `pd16_select` writer - PD16 Select"]
95pub type PD16_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PD16_SELECT_A>;
96impl<'a, REG> PD16_SELECT_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99    REG::Ux: From<u8>,
100{
101    #[doc = "`0`"]
102    #[inline(always)]
103    pub fn input(self) -> &'a mut crate::W<REG> {
104        self.variant(PD16_SELECT_A::INPUT)
105    }
106    #[doc = "`10`"]
107    #[inline(always)]
108    pub fn lcd0_d22(self) -> &'a mut crate::W<REG> {
109        self.variant(PD16_SELECT_A::LCD0_D22)
110    }
111    #[doc = "`100`"]
112    #[inline(always)]
113    pub fn dmic_data3(self) -> &'a mut crate::W<REG> {
114        self.variant(PD16_SELECT_A::DMIC_DATA3)
115    }
116    #[doc = "`1110`"]
117    #[inline(always)]
118    pub fn pd_eint16(self) -> &'a mut crate::W<REG> {
119        self.variant(PD16_SELECT_A::PD_EINT16)
120    }
121    #[doc = "`1`"]
122    #[inline(always)]
123    pub fn output(self) -> &'a mut crate::W<REG> {
124        self.variant(PD16_SELECT_A::OUTPUT)
125    }
126    #[doc = "`11`"]
127    #[inline(always)]
128    pub fn lvds1_ckp(self) -> &'a mut crate::W<REG> {
129        self.variant(PD16_SELECT_A::LVDS1_CKP)
130    }
131    #[doc = "`101`"]
132    #[inline(always)]
133    pub fn pwm0(self) -> &'a mut crate::W<REG> {
134        self.variant(PD16_SELECT_A::PWM0)
135    }
136    #[doc = "`1111`"]
137    #[inline(always)]
138    pub fn io_disable(self) -> &'a mut crate::W<REG> {
139        self.variant(PD16_SELECT_A::IO_DISABLE)
140    }
141}
142#[doc = "Field `pd17_select` reader - PD17 Select"]
143pub type PD17_SELECT_R = crate::FieldReader<PD17_SELECT_A>;
144#[doc = "PD17 Select\n\nValue on reset: 0"]
145#[derive(Clone, Copy, Debug, PartialEq, Eq)]
146#[repr(u8)]
147pub enum PD17_SELECT_A {
148    #[doc = "0: `0`"]
149    INPUT = 0,
150    #[doc = "2: `10`"]
151    LCD0_D23 = 2,
152    #[doc = "4: `100`"]
153    DMIC_DATA2 = 4,
154    #[doc = "14: `1110`"]
155    PD_EINT17 = 14,
156    #[doc = "1: `1`"]
157    OUTPUT = 1,
158    #[doc = "3: `11`"]
159    LVDS1_CKN = 3,
160    #[doc = "5: `101`"]
161    PWM1 = 5,
162    #[doc = "15: `1111`"]
163    IO_DISABLE = 15,
164}
165impl From<PD17_SELECT_A> for u8 {
166    #[inline(always)]
167    fn from(variant: PD17_SELECT_A) -> Self {
168        variant as _
169    }
170}
171impl crate::FieldSpec for PD17_SELECT_A {
172    type Ux = u8;
173}
174impl PD17_SELECT_R {
175    #[doc = "Get enumerated values variant"]
176    #[inline(always)]
177    pub const fn variant(&self) -> Option<PD17_SELECT_A> {
178        match self.bits {
179            0 => Some(PD17_SELECT_A::INPUT),
180            2 => Some(PD17_SELECT_A::LCD0_D23),
181            4 => Some(PD17_SELECT_A::DMIC_DATA2),
182            14 => Some(PD17_SELECT_A::PD_EINT17),
183            1 => Some(PD17_SELECT_A::OUTPUT),
184            3 => Some(PD17_SELECT_A::LVDS1_CKN),
185            5 => Some(PD17_SELECT_A::PWM1),
186            15 => Some(PD17_SELECT_A::IO_DISABLE),
187            _ => None,
188        }
189    }
190    #[doc = "`0`"]
191    #[inline(always)]
192    pub fn is_input(&self) -> bool {
193        *self == PD17_SELECT_A::INPUT
194    }
195    #[doc = "`10`"]
196    #[inline(always)]
197    pub fn is_lcd0_d23(&self) -> bool {
198        *self == PD17_SELECT_A::LCD0_D23
199    }
200    #[doc = "`100`"]
201    #[inline(always)]
202    pub fn is_dmic_data2(&self) -> bool {
203        *self == PD17_SELECT_A::DMIC_DATA2
204    }
205    #[doc = "`1110`"]
206    #[inline(always)]
207    pub fn is_pd_eint17(&self) -> bool {
208        *self == PD17_SELECT_A::PD_EINT17
209    }
210    #[doc = "`1`"]
211    #[inline(always)]
212    pub fn is_output(&self) -> bool {
213        *self == PD17_SELECT_A::OUTPUT
214    }
215    #[doc = "`11`"]
216    #[inline(always)]
217    pub fn is_lvds1_ckn(&self) -> bool {
218        *self == PD17_SELECT_A::LVDS1_CKN
219    }
220    #[doc = "`101`"]
221    #[inline(always)]
222    pub fn is_pwm1(&self) -> bool {
223        *self == PD17_SELECT_A::PWM1
224    }
225    #[doc = "`1111`"]
226    #[inline(always)]
227    pub fn is_io_disable(&self) -> bool {
228        *self == PD17_SELECT_A::IO_DISABLE
229    }
230}
231#[doc = "Field `pd17_select` writer - PD17 Select"]
232pub type PD17_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PD17_SELECT_A>;
233impl<'a, REG> PD17_SELECT_W<'a, REG>
234where
235    REG: crate::Writable + crate::RegisterSpec,
236    REG::Ux: From<u8>,
237{
238    #[doc = "`0`"]
239    #[inline(always)]
240    pub fn input(self) -> &'a mut crate::W<REG> {
241        self.variant(PD17_SELECT_A::INPUT)
242    }
243    #[doc = "`10`"]
244    #[inline(always)]
245    pub fn lcd0_d23(self) -> &'a mut crate::W<REG> {
246        self.variant(PD17_SELECT_A::LCD0_D23)
247    }
248    #[doc = "`100`"]
249    #[inline(always)]
250    pub fn dmic_data2(self) -> &'a mut crate::W<REG> {
251        self.variant(PD17_SELECT_A::DMIC_DATA2)
252    }
253    #[doc = "`1110`"]
254    #[inline(always)]
255    pub fn pd_eint17(self) -> &'a mut crate::W<REG> {
256        self.variant(PD17_SELECT_A::PD_EINT17)
257    }
258    #[doc = "`1`"]
259    #[inline(always)]
260    pub fn output(self) -> &'a mut crate::W<REG> {
261        self.variant(PD17_SELECT_A::OUTPUT)
262    }
263    #[doc = "`11`"]
264    #[inline(always)]
265    pub fn lvds1_ckn(self) -> &'a mut crate::W<REG> {
266        self.variant(PD17_SELECT_A::LVDS1_CKN)
267    }
268    #[doc = "`101`"]
269    #[inline(always)]
270    pub fn pwm1(self) -> &'a mut crate::W<REG> {
271        self.variant(PD17_SELECT_A::PWM1)
272    }
273    #[doc = "`1111`"]
274    #[inline(always)]
275    pub fn io_disable(self) -> &'a mut crate::W<REG> {
276        self.variant(PD17_SELECT_A::IO_DISABLE)
277    }
278}
279#[doc = "Field `pd18_select` reader - PD18 Select"]
280pub type PD18_SELECT_R = crate::FieldReader<PD18_SELECT_A>;
281#[doc = "PD18 Select\n\nValue on reset: 0"]
282#[derive(Clone, Copy, Debug, PartialEq, Eq)]
283#[repr(u8)]
284pub enum PD18_SELECT_A {
285    #[doc = "0: `0`"]
286    INPUT = 0,
287    #[doc = "2: `10`"]
288    LCD0_CLK = 2,
289    #[doc = "4: `100`"]
290    DMIC_DATA1 = 4,
291    #[doc = "14: `1110`"]
292    PD_EINT18 = 14,
293    #[doc = "1: `1`"]
294    OUTPUT = 1,
295    #[doc = "3: `11`"]
296    LVDS1_V3P = 3,
297    #[doc = "5: `101`"]
298    PWM2 = 5,
299    #[doc = "15: `1111`"]
300    IO_DISABLE = 15,
301}
302impl From<PD18_SELECT_A> for u8 {
303    #[inline(always)]
304    fn from(variant: PD18_SELECT_A) -> Self {
305        variant as _
306    }
307}
308impl crate::FieldSpec for PD18_SELECT_A {
309    type Ux = u8;
310}
311impl PD18_SELECT_R {
312    #[doc = "Get enumerated values variant"]
313    #[inline(always)]
314    pub const fn variant(&self) -> Option<PD18_SELECT_A> {
315        match self.bits {
316            0 => Some(PD18_SELECT_A::INPUT),
317            2 => Some(PD18_SELECT_A::LCD0_CLK),
318            4 => Some(PD18_SELECT_A::DMIC_DATA1),
319            14 => Some(PD18_SELECT_A::PD_EINT18),
320            1 => Some(PD18_SELECT_A::OUTPUT),
321            3 => Some(PD18_SELECT_A::LVDS1_V3P),
322            5 => Some(PD18_SELECT_A::PWM2),
323            15 => Some(PD18_SELECT_A::IO_DISABLE),
324            _ => None,
325        }
326    }
327    #[doc = "`0`"]
328    #[inline(always)]
329    pub fn is_input(&self) -> bool {
330        *self == PD18_SELECT_A::INPUT
331    }
332    #[doc = "`10`"]
333    #[inline(always)]
334    pub fn is_lcd0_clk(&self) -> bool {
335        *self == PD18_SELECT_A::LCD0_CLK
336    }
337    #[doc = "`100`"]
338    #[inline(always)]
339    pub fn is_dmic_data1(&self) -> bool {
340        *self == PD18_SELECT_A::DMIC_DATA1
341    }
342    #[doc = "`1110`"]
343    #[inline(always)]
344    pub fn is_pd_eint18(&self) -> bool {
345        *self == PD18_SELECT_A::PD_EINT18
346    }
347    #[doc = "`1`"]
348    #[inline(always)]
349    pub fn is_output(&self) -> bool {
350        *self == PD18_SELECT_A::OUTPUT
351    }
352    #[doc = "`11`"]
353    #[inline(always)]
354    pub fn is_lvds1_v3p(&self) -> bool {
355        *self == PD18_SELECT_A::LVDS1_V3P
356    }
357    #[doc = "`101`"]
358    #[inline(always)]
359    pub fn is_pwm2(&self) -> bool {
360        *self == PD18_SELECT_A::PWM2
361    }
362    #[doc = "`1111`"]
363    #[inline(always)]
364    pub fn is_io_disable(&self) -> bool {
365        *self == PD18_SELECT_A::IO_DISABLE
366    }
367}
368#[doc = "Field `pd18_select` writer - PD18 Select"]
369pub type PD18_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PD18_SELECT_A>;
370impl<'a, REG> PD18_SELECT_W<'a, REG>
371where
372    REG: crate::Writable + crate::RegisterSpec,
373    REG::Ux: From<u8>,
374{
375    #[doc = "`0`"]
376    #[inline(always)]
377    pub fn input(self) -> &'a mut crate::W<REG> {
378        self.variant(PD18_SELECT_A::INPUT)
379    }
380    #[doc = "`10`"]
381    #[inline(always)]
382    pub fn lcd0_clk(self) -> &'a mut crate::W<REG> {
383        self.variant(PD18_SELECT_A::LCD0_CLK)
384    }
385    #[doc = "`100`"]
386    #[inline(always)]
387    pub fn dmic_data1(self) -> &'a mut crate::W<REG> {
388        self.variant(PD18_SELECT_A::DMIC_DATA1)
389    }
390    #[doc = "`1110`"]
391    #[inline(always)]
392    pub fn pd_eint18(self) -> &'a mut crate::W<REG> {
393        self.variant(PD18_SELECT_A::PD_EINT18)
394    }
395    #[doc = "`1`"]
396    #[inline(always)]
397    pub fn output(self) -> &'a mut crate::W<REG> {
398        self.variant(PD18_SELECT_A::OUTPUT)
399    }
400    #[doc = "`11`"]
401    #[inline(always)]
402    pub fn lvds1_v3p(self) -> &'a mut crate::W<REG> {
403        self.variant(PD18_SELECT_A::LVDS1_V3P)
404    }
405    #[doc = "`101`"]
406    #[inline(always)]
407    pub fn pwm2(self) -> &'a mut crate::W<REG> {
408        self.variant(PD18_SELECT_A::PWM2)
409    }
410    #[doc = "`1111`"]
411    #[inline(always)]
412    pub fn io_disable(self) -> &'a mut crate::W<REG> {
413        self.variant(PD18_SELECT_A::IO_DISABLE)
414    }
415}
416#[doc = "Field `pd19_select` reader - PD19 Select"]
417pub type PD19_SELECT_R = crate::FieldReader<PD19_SELECT_A>;
418#[doc = "PD19 Select\n\nValue on reset: 0"]
419#[derive(Clone, Copy, Debug, PartialEq, Eq)]
420#[repr(u8)]
421pub enum PD19_SELECT_A {
422    #[doc = "0: `0`"]
423    INPUT = 0,
424    #[doc = "2: `10`"]
425    LCD0_DE = 2,
426    #[doc = "4: `100`"]
427    DMIC_DATA0 = 4,
428    #[doc = "14: `1110`"]
429    PD_EINT19 = 14,
430    #[doc = "1: `1`"]
431    OUTPUT = 1,
432    #[doc = "3: `11`"]
433    LVDS1_V3N = 3,
434    #[doc = "5: `101`"]
435    PWM3 = 5,
436    #[doc = "15: `1111`"]
437    IO_DISABLE = 15,
438}
439impl From<PD19_SELECT_A> for u8 {
440    #[inline(always)]
441    fn from(variant: PD19_SELECT_A) -> Self {
442        variant as _
443    }
444}
445impl crate::FieldSpec for PD19_SELECT_A {
446    type Ux = u8;
447}
448impl PD19_SELECT_R {
449    #[doc = "Get enumerated values variant"]
450    #[inline(always)]
451    pub const fn variant(&self) -> Option<PD19_SELECT_A> {
452        match self.bits {
453            0 => Some(PD19_SELECT_A::INPUT),
454            2 => Some(PD19_SELECT_A::LCD0_DE),
455            4 => Some(PD19_SELECT_A::DMIC_DATA0),
456            14 => Some(PD19_SELECT_A::PD_EINT19),
457            1 => Some(PD19_SELECT_A::OUTPUT),
458            3 => Some(PD19_SELECT_A::LVDS1_V3N),
459            5 => Some(PD19_SELECT_A::PWM3),
460            15 => Some(PD19_SELECT_A::IO_DISABLE),
461            _ => None,
462        }
463    }
464    #[doc = "`0`"]
465    #[inline(always)]
466    pub fn is_input(&self) -> bool {
467        *self == PD19_SELECT_A::INPUT
468    }
469    #[doc = "`10`"]
470    #[inline(always)]
471    pub fn is_lcd0_de(&self) -> bool {
472        *self == PD19_SELECT_A::LCD0_DE
473    }
474    #[doc = "`100`"]
475    #[inline(always)]
476    pub fn is_dmic_data0(&self) -> bool {
477        *self == PD19_SELECT_A::DMIC_DATA0
478    }
479    #[doc = "`1110`"]
480    #[inline(always)]
481    pub fn is_pd_eint19(&self) -> bool {
482        *self == PD19_SELECT_A::PD_EINT19
483    }
484    #[doc = "`1`"]
485    #[inline(always)]
486    pub fn is_output(&self) -> bool {
487        *self == PD19_SELECT_A::OUTPUT
488    }
489    #[doc = "`11`"]
490    #[inline(always)]
491    pub fn is_lvds1_v3n(&self) -> bool {
492        *self == PD19_SELECT_A::LVDS1_V3N
493    }
494    #[doc = "`101`"]
495    #[inline(always)]
496    pub fn is_pwm3(&self) -> bool {
497        *self == PD19_SELECT_A::PWM3
498    }
499    #[doc = "`1111`"]
500    #[inline(always)]
501    pub fn is_io_disable(&self) -> bool {
502        *self == PD19_SELECT_A::IO_DISABLE
503    }
504}
505#[doc = "Field `pd19_select` writer - PD19 Select"]
506pub type PD19_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PD19_SELECT_A>;
507impl<'a, REG> PD19_SELECT_W<'a, REG>
508where
509    REG: crate::Writable + crate::RegisterSpec,
510    REG::Ux: From<u8>,
511{
512    #[doc = "`0`"]
513    #[inline(always)]
514    pub fn input(self) -> &'a mut crate::W<REG> {
515        self.variant(PD19_SELECT_A::INPUT)
516    }
517    #[doc = "`10`"]
518    #[inline(always)]
519    pub fn lcd0_de(self) -> &'a mut crate::W<REG> {
520        self.variant(PD19_SELECT_A::LCD0_DE)
521    }
522    #[doc = "`100`"]
523    #[inline(always)]
524    pub fn dmic_data0(self) -> &'a mut crate::W<REG> {
525        self.variant(PD19_SELECT_A::DMIC_DATA0)
526    }
527    #[doc = "`1110`"]
528    #[inline(always)]
529    pub fn pd_eint19(self) -> &'a mut crate::W<REG> {
530        self.variant(PD19_SELECT_A::PD_EINT19)
531    }
532    #[doc = "`1`"]
533    #[inline(always)]
534    pub fn output(self) -> &'a mut crate::W<REG> {
535        self.variant(PD19_SELECT_A::OUTPUT)
536    }
537    #[doc = "`11`"]
538    #[inline(always)]
539    pub fn lvds1_v3n(self) -> &'a mut crate::W<REG> {
540        self.variant(PD19_SELECT_A::LVDS1_V3N)
541    }
542    #[doc = "`101`"]
543    #[inline(always)]
544    pub fn pwm3(self) -> &'a mut crate::W<REG> {
545        self.variant(PD19_SELECT_A::PWM3)
546    }
547    #[doc = "`1111`"]
548    #[inline(always)]
549    pub fn io_disable(self) -> &'a mut crate::W<REG> {
550        self.variant(PD19_SELECT_A::IO_DISABLE)
551    }
552}
553#[doc = "Field `pd20_select` reader - PD20 Select"]
554pub type PD20_SELECT_R = crate::FieldReader<PD20_SELECT_A>;
555#[doc = "PD20 Select\n\nValue on reset: 0"]
556#[derive(Clone, Copy, Debug, PartialEq, Eq)]
557#[repr(u8)]
558pub enum PD20_SELECT_A {
559    #[doc = "0: `0`"]
560    INPUT = 0,
561    #[doc = "2: `10`"]
562    LCD0_HSYNC = 2,
563    #[doc = "4: `100`"]
564    DMIC_CLK = 4,
565    #[doc = "14: `1110`"]
566    PD_EINT20 = 14,
567    #[doc = "1: `1`"]
568    OUTPUT = 1,
569    #[doc = "3: `11`"]
570    TWI2_SCK = 3,
571    #[doc = "5: `101`"]
572    PWM4 = 5,
573    #[doc = "15: `1111`"]
574    IO_DISABLE = 15,
575}
576impl From<PD20_SELECT_A> for u8 {
577    #[inline(always)]
578    fn from(variant: PD20_SELECT_A) -> Self {
579        variant as _
580    }
581}
582impl crate::FieldSpec for PD20_SELECT_A {
583    type Ux = u8;
584}
585impl PD20_SELECT_R {
586    #[doc = "Get enumerated values variant"]
587    #[inline(always)]
588    pub const fn variant(&self) -> Option<PD20_SELECT_A> {
589        match self.bits {
590            0 => Some(PD20_SELECT_A::INPUT),
591            2 => Some(PD20_SELECT_A::LCD0_HSYNC),
592            4 => Some(PD20_SELECT_A::DMIC_CLK),
593            14 => Some(PD20_SELECT_A::PD_EINT20),
594            1 => Some(PD20_SELECT_A::OUTPUT),
595            3 => Some(PD20_SELECT_A::TWI2_SCK),
596            5 => Some(PD20_SELECT_A::PWM4),
597            15 => Some(PD20_SELECT_A::IO_DISABLE),
598            _ => None,
599        }
600    }
601    #[doc = "`0`"]
602    #[inline(always)]
603    pub fn is_input(&self) -> bool {
604        *self == PD20_SELECT_A::INPUT
605    }
606    #[doc = "`10`"]
607    #[inline(always)]
608    pub fn is_lcd0_hsync(&self) -> bool {
609        *self == PD20_SELECT_A::LCD0_HSYNC
610    }
611    #[doc = "`100`"]
612    #[inline(always)]
613    pub fn is_dmic_clk(&self) -> bool {
614        *self == PD20_SELECT_A::DMIC_CLK
615    }
616    #[doc = "`1110`"]
617    #[inline(always)]
618    pub fn is_pd_eint20(&self) -> bool {
619        *self == PD20_SELECT_A::PD_EINT20
620    }
621    #[doc = "`1`"]
622    #[inline(always)]
623    pub fn is_output(&self) -> bool {
624        *self == PD20_SELECT_A::OUTPUT
625    }
626    #[doc = "`11`"]
627    #[inline(always)]
628    pub fn is_twi2_sck(&self) -> bool {
629        *self == PD20_SELECT_A::TWI2_SCK
630    }
631    #[doc = "`101`"]
632    #[inline(always)]
633    pub fn is_pwm4(&self) -> bool {
634        *self == PD20_SELECT_A::PWM4
635    }
636    #[doc = "`1111`"]
637    #[inline(always)]
638    pub fn is_io_disable(&self) -> bool {
639        *self == PD20_SELECT_A::IO_DISABLE
640    }
641}
642#[doc = "Field `pd20_select` writer - PD20 Select"]
643pub type PD20_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PD20_SELECT_A>;
644impl<'a, REG> PD20_SELECT_W<'a, REG>
645where
646    REG: crate::Writable + crate::RegisterSpec,
647    REG::Ux: From<u8>,
648{
649    #[doc = "`0`"]
650    #[inline(always)]
651    pub fn input(self) -> &'a mut crate::W<REG> {
652        self.variant(PD20_SELECT_A::INPUT)
653    }
654    #[doc = "`10`"]
655    #[inline(always)]
656    pub fn lcd0_hsync(self) -> &'a mut crate::W<REG> {
657        self.variant(PD20_SELECT_A::LCD0_HSYNC)
658    }
659    #[doc = "`100`"]
660    #[inline(always)]
661    pub fn dmic_clk(self) -> &'a mut crate::W<REG> {
662        self.variant(PD20_SELECT_A::DMIC_CLK)
663    }
664    #[doc = "`1110`"]
665    #[inline(always)]
666    pub fn pd_eint20(self) -> &'a mut crate::W<REG> {
667        self.variant(PD20_SELECT_A::PD_EINT20)
668    }
669    #[doc = "`1`"]
670    #[inline(always)]
671    pub fn output(self) -> &'a mut crate::W<REG> {
672        self.variant(PD20_SELECT_A::OUTPUT)
673    }
674    #[doc = "`11`"]
675    #[inline(always)]
676    pub fn twi2_sck(self) -> &'a mut crate::W<REG> {
677        self.variant(PD20_SELECT_A::TWI2_SCK)
678    }
679    #[doc = "`101`"]
680    #[inline(always)]
681    pub fn pwm4(self) -> &'a mut crate::W<REG> {
682        self.variant(PD20_SELECT_A::PWM4)
683    }
684    #[doc = "`1111`"]
685    #[inline(always)]
686    pub fn io_disable(self) -> &'a mut crate::W<REG> {
687        self.variant(PD20_SELECT_A::IO_DISABLE)
688    }
689}
690#[doc = "Field `pd21_select` reader - PD21 Select"]
691pub type PD21_SELECT_R = crate::FieldReader<PD21_SELECT_A>;
692#[doc = "PD21 Select\n\nValue on reset: 0"]
693#[derive(Clone, Copy, Debug, PartialEq, Eq)]
694#[repr(u8)]
695pub enum PD21_SELECT_A {
696    #[doc = "0: `0`"]
697    INPUT = 0,
698    #[doc = "2: `10`"]
699    LCD0_VSYNC = 2,
700    #[doc = "4: `100`"]
701    UART1_TX = 4,
702    #[doc = "14: `1110`"]
703    PD_EINT21 = 14,
704    #[doc = "1: `1`"]
705    OUTPUT = 1,
706    #[doc = "3: `11`"]
707    TWI2_SDA = 3,
708    #[doc = "5: `101`"]
709    PWM5 = 5,
710    #[doc = "15: `1111`"]
711    IO_DISABLE = 15,
712}
713impl From<PD21_SELECT_A> for u8 {
714    #[inline(always)]
715    fn from(variant: PD21_SELECT_A) -> Self {
716        variant as _
717    }
718}
719impl crate::FieldSpec for PD21_SELECT_A {
720    type Ux = u8;
721}
722impl PD21_SELECT_R {
723    #[doc = "Get enumerated values variant"]
724    #[inline(always)]
725    pub const fn variant(&self) -> Option<PD21_SELECT_A> {
726        match self.bits {
727            0 => Some(PD21_SELECT_A::INPUT),
728            2 => Some(PD21_SELECT_A::LCD0_VSYNC),
729            4 => Some(PD21_SELECT_A::UART1_TX),
730            14 => Some(PD21_SELECT_A::PD_EINT21),
731            1 => Some(PD21_SELECT_A::OUTPUT),
732            3 => Some(PD21_SELECT_A::TWI2_SDA),
733            5 => Some(PD21_SELECT_A::PWM5),
734            15 => Some(PD21_SELECT_A::IO_DISABLE),
735            _ => None,
736        }
737    }
738    #[doc = "`0`"]
739    #[inline(always)]
740    pub fn is_input(&self) -> bool {
741        *self == PD21_SELECT_A::INPUT
742    }
743    #[doc = "`10`"]
744    #[inline(always)]
745    pub fn is_lcd0_vsync(&self) -> bool {
746        *self == PD21_SELECT_A::LCD0_VSYNC
747    }
748    #[doc = "`100`"]
749    #[inline(always)]
750    pub fn is_uart1_tx(&self) -> bool {
751        *self == PD21_SELECT_A::UART1_TX
752    }
753    #[doc = "`1110`"]
754    #[inline(always)]
755    pub fn is_pd_eint21(&self) -> bool {
756        *self == PD21_SELECT_A::PD_EINT21
757    }
758    #[doc = "`1`"]
759    #[inline(always)]
760    pub fn is_output(&self) -> bool {
761        *self == PD21_SELECT_A::OUTPUT
762    }
763    #[doc = "`11`"]
764    #[inline(always)]
765    pub fn is_twi2_sda(&self) -> bool {
766        *self == PD21_SELECT_A::TWI2_SDA
767    }
768    #[doc = "`101`"]
769    #[inline(always)]
770    pub fn is_pwm5(&self) -> bool {
771        *self == PD21_SELECT_A::PWM5
772    }
773    #[doc = "`1111`"]
774    #[inline(always)]
775    pub fn is_io_disable(&self) -> bool {
776        *self == PD21_SELECT_A::IO_DISABLE
777    }
778}
779#[doc = "Field `pd21_select` writer - PD21 Select"]
780pub type PD21_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PD21_SELECT_A>;
781impl<'a, REG> PD21_SELECT_W<'a, REG>
782where
783    REG: crate::Writable + crate::RegisterSpec,
784    REG::Ux: From<u8>,
785{
786    #[doc = "`0`"]
787    #[inline(always)]
788    pub fn input(self) -> &'a mut crate::W<REG> {
789        self.variant(PD21_SELECT_A::INPUT)
790    }
791    #[doc = "`10`"]
792    #[inline(always)]
793    pub fn lcd0_vsync(self) -> &'a mut crate::W<REG> {
794        self.variant(PD21_SELECT_A::LCD0_VSYNC)
795    }
796    #[doc = "`100`"]
797    #[inline(always)]
798    pub fn uart1_tx(self) -> &'a mut crate::W<REG> {
799        self.variant(PD21_SELECT_A::UART1_TX)
800    }
801    #[doc = "`1110`"]
802    #[inline(always)]
803    pub fn pd_eint21(self) -> &'a mut crate::W<REG> {
804        self.variant(PD21_SELECT_A::PD_EINT21)
805    }
806    #[doc = "`1`"]
807    #[inline(always)]
808    pub fn output(self) -> &'a mut crate::W<REG> {
809        self.variant(PD21_SELECT_A::OUTPUT)
810    }
811    #[doc = "`11`"]
812    #[inline(always)]
813    pub fn twi2_sda(self) -> &'a mut crate::W<REG> {
814        self.variant(PD21_SELECT_A::TWI2_SDA)
815    }
816    #[doc = "`101`"]
817    #[inline(always)]
818    pub fn pwm5(self) -> &'a mut crate::W<REG> {
819        self.variant(PD21_SELECT_A::PWM5)
820    }
821    #[doc = "`1111`"]
822    #[inline(always)]
823    pub fn io_disable(self) -> &'a mut crate::W<REG> {
824        self.variant(PD21_SELECT_A::IO_DISABLE)
825    }
826}
827#[doc = "Field `pd22_select` reader - PD22 Select"]
828pub type PD22_SELECT_R = crate::FieldReader<PD22_SELECT_A>;
829#[doc = "PD22 Select\n\nValue on reset: 0"]
830#[derive(Clone, Copy, Debug, PartialEq, Eq)]
831#[repr(u8)]
832pub enum PD22_SELECT_A {
833    #[doc = "0: `0`"]
834    INPUT = 0,
835    #[doc = "2: `10`"]
836    OWA_OUT = 2,
837    #[doc = "4: `100`"]
838    UART1_RX = 4,
839    #[doc = "14: `1110`"]
840    PD_EINT22 = 14,
841    #[doc = "1: `1`"]
842    OUTPUT = 1,
843    #[doc = "3: `11`"]
844    IR_RX = 3,
845    #[doc = "5: `101`"]
846    PWM7 = 5,
847    #[doc = "15: `1111`"]
848    IO_DISABLE = 15,
849}
850impl From<PD22_SELECT_A> for u8 {
851    #[inline(always)]
852    fn from(variant: PD22_SELECT_A) -> Self {
853        variant as _
854    }
855}
856impl crate::FieldSpec for PD22_SELECT_A {
857    type Ux = u8;
858}
859impl PD22_SELECT_R {
860    #[doc = "Get enumerated values variant"]
861    #[inline(always)]
862    pub const fn variant(&self) -> Option<PD22_SELECT_A> {
863        match self.bits {
864            0 => Some(PD22_SELECT_A::INPUT),
865            2 => Some(PD22_SELECT_A::OWA_OUT),
866            4 => Some(PD22_SELECT_A::UART1_RX),
867            14 => Some(PD22_SELECT_A::PD_EINT22),
868            1 => Some(PD22_SELECT_A::OUTPUT),
869            3 => Some(PD22_SELECT_A::IR_RX),
870            5 => Some(PD22_SELECT_A::PWM7),
871            15 => Some(PD22_SELECT_A::IO_DISABLE),
872            _ => None,
873        }
874    }
875    #[doc = "`0`"]
876    #[inline(always)]
877    pub fn is_input(&self) -> bool {
878        *self == PD22_SELECT_A::INPUT
879    }
880    #[doc = "`10`"]
881    #[inline(always)]
882    pub fn is_owa_out(&self) -> bool {
883        *self == PD22_SELECT_A::OWA_OUT
884    }
885    #[doc = "`100`"]
886    #[inline(always)]
887    pub fn is_uart1_rx(&self) -> bool {
888        *self == PD22_SELECT_A::UART1_RX
889    }
890    #[doc = "`1110`"]
891    #[inline(always)]
892    pub fn is_pd_eint22(&self) -> bool {
893        *self == PD22_SELECT_A::PD_EINT22
894    }
895    #[doc = "`1`"]
896    #[inline(always)]
897    pub fn is_output(&self) -> bool {
898        *self == PD22_SELECT_A::OUTPUT
899    }
900    #[doc = "`11`"]
901    #[inline(always)]
902    pub fn is_ir_rx(&self) -> bool {
903        *self == PD22_SELECT_A::IR_RX
904    }
905    #[doc = "`101`"]
906    #[inline(always)]
907    pub fn is_pwm7(&self) -> bool {
908        *self == PD22_SELECT_A::PWM7
909    }
910    #[doc = "`1111`"]
911    #[inline(always)]
912    pub fn is_io_disable(&self) -> bool {
913        *self == PD22_SELECT_A::IO_DISABLE
914    }
915}
916#[doc = "Field `pd22_select` writer - PD22 Select"]
917pub type PD22_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PD22_SELECT_A>;
918impl<'a, REG> PD22_SELECT_W<'a, REG>
919where
920    REG: crate::Writable + crate::RegisterSpec,
921    REG::Ux: From<u8>,
922{
923    #[doc = "`0`"]
924    #[inline(always)]
925    pub fn input(self) -> &'a mut crate::W<REG> {
926        self.variant(PD22_SELECT_A::INPUT)
927    }
928    #[doc = "`10`"]
929    #[inline(always)]
930    pub fn owa_out(self) -> &'a mut crate::W<REG> {
931        self.variant(PD22_SELECT_A::OWA_OUT)
932    }
933    #[doc = "`100`"]
934    #[inline(always)]
935    pub fn uart1_rx(self) -> &'a mut crate::W<REG> {
936        self.variant(PD22_SELECT_A::UART1_RX)
937    }
938    #[doc = "`1110`"]
939    #[inline(always)]
940    pub fn pd_eint22(self) -> &'a mut crate::W<REG> {
941        self.variant(PD22_SELECT_A::PD_EINT22)
942    }
943    #[doc = "`1`"]
944    #[inline(always)]
945    pub fn output(self) -> &'a mut crate::W<REG> {
946        self.variant(PD22_SELECT_A::OUTPUT)
947    }
948    #[doc = "`11`"]
949    #[inline(always)]
950    pub fn ir_rx(self) -> &'a mut crate::W<REG> {
951        self.variant(PD22_SELECT_A::IR_RX)
952    }
953    #[doc = "`101`"]
954    #[inline(always)]
955    pub fn pwm7(self) -> &'a mut crate::W<REG> {
956        self.variant(PD22_SELECT_A::PWM7)
957    }
958    #[doc = "`1111`"]
959    #[inline(always)]
960    pub fn io_disable(self) -> &'a mut crate::W<REG> {
961        self.variant(PD22_SELECT_A::IO_DISABLE)
962    }
963}
964impl R {
965    #[doc = "Bits 0:3 - PD16 Select"]
966    #[inline(always)]
967    pub fn pd16_select(&self) -> PD16_SELECT_R {
968        PD16_SELECT_R::new((self.bits & 0x0f) as u8)
969    }
970    #[doc = "Bits 4:7 - PD17 Select"]
971    #[inline(always)]
972    pub fn pd17_select(&self) -> PD17_SELECT_R {
973        PD17_SELECT_R::new(((self.bits >> 4) & 0x0f) as u8)
974    }
975    #[doc = "Bits 8:11 - PD18 Select"]
976    #[inline(always)]
977    pub fn pd18_select(&self) -> PD18_SELECT_R {
978        PD18_SELECT_R::new(((self.bits >> 8) & 0x0f) as u8)
979    }
980    #[doc = "Bits 12:15 - PD19 Select"]
981    #[inline(always)]
982    pub fn pd19_select(&self) -> PD19_SELECT_R {
983        PD19_SELECT_R::new(((self.bits >> 12) & 0x0f) as u8)
984    }
985    #[doc = "Bits 16:19 - PD20 Select"]
986    #[inline(always)]
987    pub fn pd20_select(&self) -> PD20_SELECT_R {
988        PD20_SELECT_R::new(((self.bits >> 16) & 0x0f) as u8)
989    }
990    #[doc = "Bits 20:23 - PD21 Select"]
991    #[inline(always)]
992    pub fn pd21_select(&self) -> PD21_SELECT_R {
993        PD21_SELECT_R::new(((self.bits >> 20) & 0x0f) as u8)
994    }
995    #[doc = "Bits 24:27 - PD22 Select"]
996    #[inline(always)]
997    pub fn pd22_select(&self) -> PD22_SELECT_R {
998        PD22_SELECT_R::new(((self.bits >> 24) & 0x0f) as u8)
999    }
1000}
1001impl W {
1002    #[doc = "Bits 0:3 - PD16 Select"]
1003    #[inline(always)]
1004    #[must_use]
1005    pub fn pd16_select(&mut self) -> PD16_SELECT_W<PD_CFG2_SPEC> {
1006        PD16_SELECT_W::new(self, 0)
1007    }
1008    #[doc = "Bits 4:7 - PD17 Select"]
1009    #[inline(always)]
1010    #[must_use]
1011    pub fn pd17_select(&mut self) -> PD17_SELECT_W<PD_CFG2_SPEC> {
1012        PD17_SELECT_W::new(self, 4)
1013    }
1014    #[doc = "Bits 8:11 - PD18 Select"]
1015    #[inline(always)]
1016    #[must_use]
1017    pub fn pd18_select(&mut self) -> PD18_SELECT_W<PD_CFG2_SPEC> {
1018        PD18_SELECT_W::new(self, 8)
1019    }
1020    #[doc = "Bits 12:15 - PD19 Select"]
1021    #[inline(always)]
1022    #[must_use]
1023    pub fn pd19_select(&mut self) -> PD19_SELECT_W<PD_CFG2_SPEC> {
1024        PD19_SELECT_W::new(self, 12)
1025    }
1026    #[doc = "Bits 16:19 - PD20 Select"]
1027    #[inline(always)]
1028    #[must_use]
1029    pub fn pd20_select(&mut self) -> PD20_SELECT_W<PD_CFG2_SPEC> {
1030        PD20_SELECT_W::new(self, 16)
1031    }
1032    #[doc = "Bits 20:23 - PD21 Select"]
1033    #[inline(always)]
1034    #[must_use]
1035    pub fn pd21_select(&mut self) -> PD21_SELECT_W<PD_CFG2_SPEC> {
1036        PD21_SELECT_W::new(self, 20)
1037    }
1038    #[doc = "Bits 24:27 - PD22 Select"]
1039    #[inline(always)]
1040    #[must_use]
1041    pub fn pd22_select(&mut self) -> PD22_SELECT_W<PD_CFG2_SPEC> {
1042        PD22_SELECT_W::new(self, 24)
1043    }
1044    #[doc = r" Writes raw bits to the register."]
1045    #[doc = r""]
1046    #[doc = r" # Safety"]
1047    #[doc = r""]
1048    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
1049    #[inline(always)]
1050    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1051        self.bits = bits;
1052        self
1053    }
1054}
1055#[doc = "PD Configure Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pd_cfg2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pd_cfg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1056pub struct PD_CFG2_SPEC;
1057impl crate::RegisterSpec for PD_CFG2_SPEC {
1058    type Ux = u32;
1059}
1060#[doc = "`read()` method returns [`pd_cfg2::R`](R) reader structure"]
1061impl crate::Readable for PD_CFG2_SPEC {}
1062#[doc = "`write(|w| ..)` method takes [`pd_cfg2::W`](W) writer structure"]
1063impl crate::Writable for PD_CFG2_SPEC {
1064    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1065    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1066}
1067#[doc = "`reset()` method sets pd_cfg2 to value 0"]
1068impl crate::Resettable for PD_CFG2_SPEC {
1069    const RESET_VALUE: Self::Ux = 0;
1070}
d1_pac/gpio/pd_cfg2.rs

d1_pac/gpio/
pd_cfg2.rs
