d1_pac/gpio/
pc_pull0.rs

1#[doc = "Register `pc_pull0` reader"]
2pub type R = crate::R<PC_PULL0_SPEC>;
3#[doc = "Register `pc_pull0` writer"]
4pub type W = crate::W<PC_PULL0_SPEC>;
5#[doc = "Field `pc_pull[0-7]` reader - PC Pull_up/down Select"]
6pub type PC_PULL_R = crate::FieldReader<PC_PULL_A>;
7#[doc = "PC Pull_up/down Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum PC_PULL_A {
11    #[doc = "0: `0`"]
12    PULL_DISABLE = 0,
13    #[doc = "1: `1`"]
14    PULL_UP = 1,
15    #[doc = "2: `10`"]
16    PULL_DOWN = 2,
17}
18impl From<PC_PULL_A> for u8 {
19    #[inline(always)]
20    fn from(variant: PC_PULL_A) -> Self {
21        variant as _
22    }
23}
24impl crate::FieldSpec for PC_PULL_A {
25    type Ux = u8;
26}
27impl PC_PULL_R {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> PC_PULL_A {
31        match self.bits {
32            0 => PC_PULL_A::PULL_DISABLE,
33            1 => PC_PULL_A::PULL_UP,
34            2 => PC_PULL_A::PULL_DOWN,
35            _ => unreachable!(),
36        }
37    }
38    #[doc = "`0`"]
39    #[inline(always)]
40    pub fn is_pull_disable(&self) -> bool {
41        *self == PC_PULL_A::PULL_DISABLE
42    }
43    #[doc = "`1`"]
44    #[inline(always)]
45    pub fn is_pull_up(&self) -> bool {
46        *self == PC_PULL_A::PULL_UP
47    }
48    #[doc = "`10`"]
49    #[inline(always)]
50    pub fn is_pull_down(&self) -> bool {
51        *self == PC_PULL_A::PULL_DOWN
52    }
53}
54#[doc = "Field `pc_pull[0-7]` writer - PC Pull_up/down Select"]
55pub type PC_PULL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PC_PULL_A>;
56impl<'a, REG> PC_PULL_W<'a, REG>
57where
58    REG: crate::Writable + crate::RegisterSpec,
59    REG::Ux: From<u8>,
60{
61    #[doc = "`0`"]
62    #[inline(always)]
63    pub fn pull_disable(self) -> &'a mut crate::W<REG> {
64        self.variant(PC_PULL_A::PULL_DISABLE)
65    }
66    #[doc = "`1`"]
67    #[inline(always)]
68    pub fn pull_up(self) -> &'a mut crate::W<REG> {
69        self.variant(PC_PULL_A::PULL_UP)
70    }
71    #[doc = "`10`"]
72    #[inline(always)]
73    pub fn pull_down(self) -> &'a mut crate::W<REG> {
74        self.variant(PC_PULL_A::PULL_DOWN)
75    }
76}
77impl R {
78    #[doc = "PC Pull_up/down Select\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pc0_pull` field"]
79    #[inline(always)]
80    pub fn pc_pull(&self, n: u8) -> PC_PULL_R {
81        #[allow(clippy::no_effect)]
82        [(); 8][n as usize];
83        PC_PULL_R::new(((self.bits >> (n * 2)) & 3) as u8)
84    }
85    #[doc = "Bits 0:1 - PC Pull_up/down Select"]
86    #[inline(always)]
87    pub fn pc0_pull(&self) -> PC_PULL_R {
88        PC_PULL_R::new((self.bits & 3) as u8)
89    }
90    #[doc = "Bits 2:3 - PC Pull_up/down Select"]
91    #[inline(always)]
92    pub fn pc1_pull(&self) -> PC_PULL_R {
93        PC_PULL_R::new(((self.bits >> 2) & 3) as u8)
94    }
95    #[doc = "Bits 4:5 - PC Pull_up/down Select"]
96    #[inline(always)]
97    pub fn pc2_pull(&self) -> PC_PULL_R {
98        PC_PULL_R::new(((self.bits >> 4) & 3) as u8)
99    }
100    #[doc = "Bits 6:7 - PC Pull_up/down Select"]
101    #[inline(always)]
102    pub fn pc3_pull(&self) -> PC_PULL_R {
103        PC_PULL_R::new(((self.bits >> 6) & 3) as u8)
104    }
105    #[doc = "Bits 8:9 - PC Pull_up/down Select"]
106    #[inline(always)]
107    pub fn pc4_pull(&self) -> PC_PULL_R {
108        PC_PULL_R::new(((self.bits >> 8) & 3) as u8)
109    }
110    #[doc = "Bits 10:11 - PC Pull_up/down Select"]
111    #[inline(always)]
112    pub fn pc5_pull(&self) -> PC_PULL_R {
113        PC_PULL_R::new(((self.bits >> 10) & 3) as u8)
114    }
115    #[doc = "Bits 12:13 - PC Pull_up/down Select"]
116    #[inline(always)]
117    pub fn pc6_pull(&self) -> PC_PULL_R {
118        PC_PULL_R::new(((self.bits >> 12) & 3) as u8)
119    }
120    #[doc = "Bits 14:15 - PC Pull_up/down Select"]
121    #[inline(always)]
122    pub fn pc7_pull(&self) -> PC_PULL_R {
123        PC_PULL_R::new(((self.bits >> 14) & 3) as u8)
124    }
125}
126impl W {
127    #[doc = "PC Pull_up/down Select\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pc0_pull` field"]
128    #[inline(always)]
129    #[must_use]
130    pub fn pc_pull(&mut self, n: u8) -> PC_PULL_W<PC_PULL0_SPEC> {
131        #[allow(clippy::no_effect)]
132        [(); 8][n as usize];
133        PC_PULL_W::new(self, n * 2)
134    }
135    #[doc = "Bits 0:1 - PC Pull_up/down Select"]
136    #[inline(always)]
137    #[must_use]
138    pub fn pc0_pull(&mut self) -> PC_PULL_W<PC_PULL0_SPEC> {
139        PC_PULL_W::new(self, 0)
140    }
141    #[doc = "Bits 2:3 - PC Pull_up/down Select"]
142    #[inline(always)]
143    #[must_use]
144    pub fn pc1_pull(&mut self) -> PC_PULL_W<PC_PULL0_SPEC> {
145        PC_PULL_W::new(self, 2)
146    }
147    #[doc = "Bits 4:5 - PC Pull_up/down Select"]
148    #[inline(always)]
149    #[must_use]
150    pub fn pc2_pull(&mut self) -> PC_PULL_W<PC_PULL0_SPEC> {
151        PC_PULL_W::new(self, 4)
152    }
153    #[doc = "Bits 6:7 - PC Pull_up/down Select"]
154    #[inline(always)]
155    #[must_use]
156    pub fn pc3_pull(&mut self) -> PC_PULL_W<PC_PULL0_SPEC> {
157        PC_PULL_W::new(self, 6)
158    }
159    #[doc = "Bits 8:9 - PC Pull_up/down Select"]
160    #[inline(always)]
161    #[must_use]
162    pub fn pc4_pull(&mut self) -> PC_PULL_W<PC_PULL0_SPEC> {
163        PC_PULL_W::new(self, 8)
164    }
165    #[doc = "Bits 10:11 - PC Pull_up/down Select"]
166    #[inline(always)]
167    #[must_use]
168    pub fn pc5_pull(&mut self) -> PC_PULL_W<PC_PULL0_SPEC> {
169        PC_PULL_W::new(self, 10)
170    }
171    #[doc = "Bits 12:13 - PC Pull_up/down Select"]
172    #[inline(always)]
173    #[must_use]
174    pub fn pc6_pull(&mut self) -> PC_PULL_W<PC_PULL0_SPEC> {
175        PC_PULL_W::new(self, 12)
176    }
177    #[doc = "Bits 14:15 - PC Pull_up/down Select"]
178    #[inline(always)]
179    #[must_use]
180    pub fn pc7_pull(&mut self) -> PC_PULL_W<PC_PULL0_SPEC> {
181        PC_PULL_W::new(self, 14)
182    }
183    #[doc = r" Writes raw bits to the register."]
184    #[doc = r""]
185    #[doc = r" # Safety"]
186    #[doc = r""]
187    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
188    #[inline(always)]
189    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
190        self.bits = bits;
191        self
192    }
193}
194#[doc = "PC Pull Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pc_pull0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pc_pull0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
195pub struct PC_PULL0_SPEC;
196impl crate::RegisterSpec for PC_PULL0_SPEC {
197    type Ux = u32;
198}
199#[doc = "`read()` method returns [`pc_pull0::R`](R) reader structure"]
200impl crate::Readable for PC_PULL0_SPEC {}
201#[doc = "`write(|w| ..)` method takes [`pc_pull0::W`](W) writer structure"]
202impl crate::Writable for PC_PULL0_SPEC {
203    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
204    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
205}
206#[doc = "`reset()` method sets pc_pull0 to value 0"]
207impl crate::Resettable for PC_PULL0_SPEC {
208    const RESET_VALUE: Self::Ux = 0;
209}