d1_pac/gpio/
pc_eint_ctl.rs

1#[doc = "Register `pc_eint_ctl` reader"]
2pub type R = crate::R<PC_EINT_CTL_SPEC>;
3#[doc = "Register `pc_eint_ctl` writer"]
4pub type W = crate::W<PC_EINT_CTL_SPEC>;
5#[doc = "Field `eint_ctl[0-7]` reader - External INT Enable"]
6pub type EINT_CTL_R = crate::BitReader<EINT_CTL_A>;
7#[doc = "External INT Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum EINT_CTL_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<EINT_CTL_A> for bool {
16    #[inline(always)]
17    fn from(variant: EINT_CTL_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl EINT_CTL_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> EINT_CTL_A {
25        match self.bits {
26            false => EINT_CTL_A::DISABLE,
27            true => EINT_CTL_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == EINT_CTL_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == EINT_CTL_A::ENABLE
39    }
40}
41#[doc = "Field `eint_ctl[0-7]` writer - External INT Enable"]
42pub type EINT_CTL_W<'a, REG> = crate::BitWriter<'a, REG, EINT_CTL_A>;
43impl<'a, REG> EINT_CTL_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(EINT_CTL_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(EINT_CTL_A::ENABLE)
56    }
57}
58impl R {
59    #[doc = "External INT Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `eint0_ctl` field"]
60    #[inline(always)]
61    pub fn eint_ctl(&self, n: u8) -> EINT_CTL_R {
62        #[allow(clippy::no_effect)]
63        [(); 8][n as usize];
64        EINT_CTL_R::new(((self.bits >> n) & 1) != 0)
65    }
66    #[doc = "Bit 0 - External INT Enable"]
67    #[inline(always)]
68    pub fn eint0_ctl(&self) -> EINT_CTL_R {
69        EINT_CTL_R::new((self.bits & 1) != 0)
70    }
71    #[doc = "Bit 1 - External INT Enable"]
72    #[inline(always)]
73    pub fn eint1_ctl(&self) -> EINT_CTL_R {
74        EINT_CTL_R::new(((self.bits >> 1) & 1) != 0)
75    }
76    #[doc = "Bit 2 - External INT Enable"]
77    #[inline(always)]
78    pub fn eint2_ctl(&self) -> EINT_CTL_R {
79        EINT_CTL_R::new(((self.bits >> 2) & 1) != 0)
80    }
81    #[doc = "Bit 3 - External INT Enable"]
82    #[inline(always)]
83    pub fn eint3_ctl(&self) -> EINT_CTL_R {
84        EINT_CTL_R::new(((self.bits >> 3) & 1) != 0)
85    }
86    #[doc = "Bit 4 - External INT Enable"]
87    #[inline(always)]
88    pub fn eint4_ctl(&self) -> EINT_CTL_R {
89        EINT_CTL_R::new(((self.bits >> 4) & 1) != 0)
90    }
91    #[doc = "Bit 5 - External INT Enable"]
92    #[inline(always)]
93    pub fn eint5_ctl(&self) -> EINT_CTL_R {
94        EINT_CTL_R::new(((self.bits >> 5) & 1) != 0)
95    }
96    #[doc = "Bit 6 - External INT Enable"]
97    #[inline(always)]
98    pub fn eint6_ctl(&self) -> EINT_CTL_R {
99        EINT_CTL_R::new(((self.bits >> 6) & 1) != 0)
100    }
101    #[doc = "Bit 7 - External INT Enable"]
102    #[inline(always)]
103    pub fn eint7_ctl(&self) -> EINT_CTL_R {
104        EINT_CTL_R::new(((self.bits >> 7) & 1) != 0)
105    }
106}
107impl W {
108    #[doc = "External INT Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `eint0_ctl` field"]
109    #[inline(always)]
110    #[must_use]
111    pub fn eint_ctl(&mut self, n: u8) -> EINT_CTL_W<PC_EINT_CTL_SPEC> {
112        #[allow(clippy::no_effect)]
113        [(); 8][n as usize];
114        EINT_CTL_W::new(self, n)
115    }
116    #[doc = "Bit 0 - External INT Enable"]
117    #[inline(always)]
118    #[must_use]
119    pub fn eint0_ctl(&mut self) -> EINT_CTL_W<PC_EINT_CTL_SPEC> {
120        EINT_CTL_W::new(self, 0)
121    }
122    #[doc = "Bit 1 - External INT Enable"]
123    #[inline(always)]
124    #[must_use]
125    pub fn eint1_ctl(&mut self) -> EINT_CTL_W<PC_EINT_CTL_SPEC> {
126        EINT_CTL_W::new(self, 1)
127    }
128    #[doc = "Bit 2 - External INT Enable"]
129    #[inline(always)]
130    #[must_use]
131    pub fn eint2_ctl(&mut self) -> EINT_CTL_W<PC_EINT_CTL_SPEC> {
132        EINT_CTL_W::new(self, 2)
133    }
134    #[doc = "Bit 3 - External INT Enable"]
135    #[inline(always)]
136    #[must_use]
137    pub fn eint3_ctl(&mut self) -> EINT_CTL_W<PC_EINT_CTL_SPEC> {
138        EINT_CTL_W::new(self, 3)
139    }
140    #[doc = "Bit 4 - External INT Enable"]
141    #[inline(always)]
142    #[must_use]
143    pub fn eint4_ctl(&mut self) -> EINT_CTL_W<PC_EINT_CTL_SPEC> {
144        EINT_CTL_W::new(self, 4)
145    }
146    #[doc = "Bit 5 - External INT Enable"]
147    #[inline(always)]
148    #[must_use]
149    pub fn eint5_ctl(&mut self) -> EINT_CTL_W<PC_EINT_CTL_SPEC> {
150        EINT_CTL_W::new(self, 5)
151    }
152    #[doc = "Bit 6 - External INT Enable"]
153    #[inline(always)]
154    #[must_use]
155    pub fn eint6_ctl(&mut self) -> EINT_CTL_W<PC_EINT_CTL_SPEC> {
156        EINT_CTL_W::new(self, 6)
157    }
158    #[doc = "Bit 7 - External INT Enable"]
159    #[inline(always)]
160    #[must_use]
161    pub fn eint7_ctl(&mut self) -> EINT_CTL_W<PC_EINT_CTL_SPEC> {
162        EINT_CTL_W::new(self, 7)
163    }
164    #[doc = r" Writes raw bits to the register."]
165    #[doc = r""]
166    #[doc = r" # Safety"]
167    #[doc = r""]
168    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
169    #[inline(always)]
170    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
171        self.bits = bits;
172        self
173    }
174}
175#[doc = "PC External Interrupt Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pc_eint_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pc_eint_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
176pub struct PC_EINT_CTL_SPEC;
177impl crate::RegisterSpec for PC_EINT_CTL_SPEC {
178    type Ux = u32;
179}
180#[doc = "`read()` method returns [`pc_eint_ctl::R`](R) reader structure"]
181impl crate::Readable for PC_EINT_CTL_SPEC {}
182#[doc = "`write(|w| ..)` method takes [`pc_eint_ctl::W`](W) writer structure"]
183impl crate::Writable for PC_EINT_CTL_SPEC {
184    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
185    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
186}
187#[doc = "`reset()` method sets pc_eint_ctl to value 0"]
188impl crate::Resettable for PC_EINT_CTL_SPEC {
189    const RESET_VALUE: Self::Ux = 0;
190}
d1_pac/gpio/pc_eint_ctl.rs

d1_pac/gpio/
pc_eint_ctl.rs
