1#[doc = "Register `pb_cfg1` reader"]
2pub type R = crate::R<PB_CFG1_SPEC>;
3#[doc = "Register `pb_cfg1` writer"]
4pub type W = crate::W<PB_CFG1_SPEC>;
5#[doc = "Field `pb8_select` reader - "]
6pub type PB8_SELECT_R = crate::FieldReader<PB8_SELECT_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum PB8_SELECT_A {
11 #[doc = "0: `0`"]
12 INPUT = 0,
13 #[doc = "1: `1`"]
14 OUTPUT = 1,
15 #[doc = "2: `10`"]
16 DMIC_DATA3 = 2,
17 #[doc = "3: `11`"]
18 PWM5 = 3,
19 #[doc = "4: `100`"]
20 TWI2_SCK = 4,
21 #[doc = "5: `101`"]
22 SPI1_HOLD_DBI_DCX_DBI_WRX = 5,
23 #[doc = "6: `110`"]
24 UART0_TX = 6,
25 #[doc = "7: `111`"]
26 UART1_TX = 7,
27 #[doc = "14: `1110`"]
28 PB_EINT8 = 14,
29 #[doc = "15: `1111`"]
30 IO_DISABLE = 15,
31}
32impl From<PB8_SELECT_A> for u8 {
33 #[inline(always)]
34 fn from(variant: PB8_SELECT_A) -> Self {
35 variant as _
36 }
37}
38impl crate::FieldSpec for PB8_SELECT_A {
39 type Ux = u8;
40}
41impl PB8_SELECT_R {
42 #[doc = "Get enumerated values variant"]
43 #[inline(always)]
44 pub const fn variant(&self) -> Option<PB8_SELECT_A> {
45 match self.bits {
46 0 => Some(PB8_SELECT_A::INPUT),
47 1 => Some(PB8_SELECT_A::OUTPUT),
48 2 => Some(PB8_SELECT_A::DMIC_DATA3),
49 3 => Some(PB8_SELECT_A::PWM5),
50 4 => Some(PB8_SELECT_A::TWI2_SCK),
51 5 => Some(PB8_SELECT_A::SPI1_HOLD_DBI_DCX_DBI_WRX),
52 6 => Some(PB8_SELECT_A::UART0_TX),
53 7 => Some(PB8_SELECT_A::UART1_TX),
54 14 => Some(PB8_SELECT_A::PB_EINT8),
55 15 => Some(PB8_SELECT_A::IO_DISABLE),
56 _ => None,
57 }
58 }
59 #[doc = "`0`"]
60 #[inline(always)]
61 pub fn is_input(&self) -> bool {
62 *self == PB8_SELECT_A::INPUT
63 }
64 #[doc = "`1`"]
65 #[inline(always)]
66 pub fn is_output(&self) -> bool {
67 *self == PB8_SELECT_A::OUTPUT
68 }
69 #[doc = "`10`"]
70 #[inline(always)]
71 pub fn is_dmic_data3(&self) -> bool {
72 *self == PB8_SELECT_A::DMIC_DATA3
73 }
74 #[doc = "`11`"]
75 #[inline(always)]
76 pub fn is_pwm5(&self) -> bool {
77 *self == PB8_SELECT_A::PWM5
78 }
79 #[doc = "`100`"]
80 #[inline(always)]
81 pub fn is_twi2_sck(&self) -> bool {
82 *self == PB8_SELECT_A::TWI2_SCK
83 }
84 #[doc = "`101`"]
85 #[inline(always)]
86 pub fn is_spi1_hold_dbi_dcx_dbi_wrx(&self) -> bool {
87 *self == PB8_SELECT_A::SPI1_HOLD_DBI_DCX_DBI_WRX
88 }
89 #[doc = "`110`"]
90 #[inline(always)]
91 pub fn is_uart0_tx(&self) -> bool {
92 *self == PB8_SELECT_A::UART0_TX
93 }
94 #[doc = "`111`"]
95 #[inline(always)]
96 pub fn is_uart1_tx(&self) -> bool {
97 *self == PB8_SELECT_A::UART1_TX
98 }
99 #[doc = "`1110`"]
100 #[inline(always)]
101 pub fn is_pb_eint8(&self) -> bool {
102 *self == PB8_SELECT_A::PB_EINT8
103 }
104 #[doc = "`1111`"]
105 #[inline(always)]
106 pub fn is_io_disable(&self) -> bool {
107 *self == PB8_SELECT_A::IO_DISABLE
108 }
109}
110#[doc = "Field `pb8_select` writer - "]
111pub type PB8_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PB8_SELECT_A>;
112impl<'a, REG> PB8_SELECT_W<'a, REG>
113where
114 REG: crate::Writable + crate::RegisterSpec,
115 REG::Ux: From<u8>,
116{
117 #[doc = "`0`"]
118 #[inline(always)]
119 pub fn input(self) -> &'a mut crate::W<REG> {
120 self.variant(PB8_SELECT_A::INPUT)
121 }
122 #[doc = "`1`"]
123 #[inline(always)]
124 pub fn output(self) -> &'a mut crate::W<REG> {
125 self.variant(PB8_SELECT_A::OUTPUT)
126 }
127 #[doc = "`10`"]
128 #[inline(always)]
129 pub fn dmic_data3(self) -> &'a mut crate::W<REG> {
130 self.variant(PB8_SELECT_A::DMIC_DATA3)
131 }
132 #[doc = "`11`"]
133 #[inline(always)]
134 pub fn pwm5(self) -> &'a mut crate::W<REG> {
135 self.variant(PB8_SELECT_A::PWM5)
136 }
137 #[doc = "`100`"]
138 #[inline(always)]
139 pub fn twi2_sck(self) -> &'a mut crate::W<REG> {
140 self.variant(PB8_SELECT_A::TWI2_SCK)
141 }
142 #[doc = "`101`"]
143 #[inline(always)]
144 pub fn spi1_hold_dbi_dcx_dbi_wrx(self) -> &'a mut crate::W<REG> {
145 self.variant(PB8_SELECT_A::SPI1_HOLD_DBI_DCX_DBI_WRX)
146 }
147 #[doc = "`110`"]
148 #[inline(always)]
149 pub fn uart0_tx(self) -> &'a mut crate::W<REG> {
150 self.variant(PB8_SELECT_A::UART0_TX)
151 }
152 #[doc = "`111`"]
153 #[inline(always)]
154 pub fn uart1_tx(self) -> &'a mut crate::W<REG> {
155 self.variant(PB8_SELECT_A::UART1_TX)
156 }
157 #[doc = "`1110`"]
158 #[inline(always)]
159 pub fn pb_eint8(self) -> &'a mut crate::W<REG> {
160 self.variant(PB8_SELECT_A::PB_EINT8)
161 }
162 #[doc = "`1111`"]
163 #[inline(always)]
164 pub fn io_disable(self) -> &'a mut crate::W<REG> {
165 self.variant(PB8_SELECT_A::IO_DISABLE)
166 }
167}
168#[doc = "Field `pb9_select` reader - "]
169pub type PB9_SELECT_R = crate::FieldReader<PB9_SELECT_A>;
170#[doc = "\n\nValue on reset: 0"]
171#[derive(Clone, Copy, Debug, PartialEq, Eq)]
172#[repr(u8)]
173pub enum PB9_SELECT_A {
174 #[doc = "0: `0`"]
175 INPUT = 0,
176 #[doc = "1: `1`"]
177 OUTPUT = 1,
178 #[doc = "2: `10`"]
179 DMIC_DATA2 = 2,
180 #[doc = "3: `11`"]
181 PWM6 = 3,
182 #[doc = "4: `100`"]
183 TWI2_SDA = 4,
184 #[doc = "5: `101`"]
185 SPI1_MISO_DBI_SDI_DBI_TE_DBI_DCX = 5,
186 #[doc = "6: `110`"]
187 UART0_RX = 6,
188 #[doc = "7: `111`"]
189 UART1_RX = 7,
190 #[doc = "14: `1110`"]
191 PB_EINT9 = 14,
192 #[doc = "15: `1111`"]
193 IO_DISABLE = 15,
194}
195impl From<PB9_SELECT_A> for u8 {
196 #[inline(always)]
197 fn from(variant: PB9_SELECT_A) -> Self {
198 variant as _
199 }
200}
201impl crate::FieldSpec for PB9_SELECT_A {
202 type Ux = u8;
203}
204impl PB9_SELECT_R {
205 #[doc = "Get enumerated values variant"]
206 #[inline(always)]
207 pub const fn variant(&self) -> Option<PB9_SELECT_A> {
208 match self.bits {
209 0 => Some(PB9_SELECT_A::INPUT),
210 1 => Some(PB9_SELECT_A::OUTPUT),
211 2 => Some(PB9_SELECT_A::DMIC_DATA2),
212 3 => Some(PB9_SELECT_A::PWM6),
213 4 => Some(PB9_SELECT_A::TWI2_SDA),
214 5 => Some(PB9_SELECT_A::SPI1_MISO_DBI_SDI_DBI_TE_DBI_DCX),
215 6 => Some(PB9_SELECT_A::UART0_RX),
216 7 => Some(PB9_SELECT_A::UART1_RX),
217 14 => Some(PB9_SELECT_A::PB_EINT9),
218 15 => Some(PB9_SELECT_A::IO_DISABLE),
219 _ => None,
220 }
221 }
222 #[doc = "`0`"]
223 #[inline(always)]
224 pub fn is_input(&self) -> bool {
225 *self == PB9_SELECT_A::INPUT
226 }
227 #[doc = "`1`"]
228 #[inline(always)]
229 pub fn is_output(&self) -> bool {
230 *self == PB9_SELECT_A::OUTPUT
231 }
232 #[doc = "`10`"]
233 #[inline(always)]
234 pub fn is_dmic_data2(&self) -> bool {
235 *self == PB9_SELECT_A::DMIC_DATA2
236 }
237 #[doc = "`11`"]
238 #[inline(always)]
239 pub fn is_pwm6(&self) -> bool {
240 *self == PB9_SELECT_A::PWM6
241 }
242 #[doc = "`100`"]
243 #[inline(always)]
244 pub fn is_twi2_sda(&self) -> bool {
245 *self == PB9_SELECT_A::TWI2_SDA
246 }
247 #[doc = "`101`"]
248 #[inline(always)]
249 pub fn is_spi1_miso_dbi_sdi_dbi_te_dbi_dcx(&self) -> bool {
250 *self == PB9_SELECT_A::SPI1_MISO_DBI_SDI_DBI_TE_DBI_DCX
251 }
252 #[doc = "`110`"]
253 #[inline(always)]
254 pub fn is_uart0_rx(&self) -> bool {
255 *self == PB9_SELECT_A::UART0_RX
256 }
257 #[doc = "`111`"]
258 #[inline(always)]
259 pub fn is_uart1_rx(&self) -> bool {
260 *self == PB9_SELECT_A::UART1_RX
261 }
262 #[doc = "`1110`"]
263 #[inline(always)]
264 pub fn is_pb_eint9(&self) -> bool {
265 *self == PB9_SELECT_A::PB_EINT9
266 }
267 #[doc = "`1111`"]
268 #[inline(always)]
269 pub fn is_io_disable(&self) -> bool {
270 *self == PB9_SELECT_A::IO_DISABLE
271 }
272}
273#[doc = "Field `pb9_select` writer - "]
274pub type PB9_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PB9_SELECT_A>;
275impl<'a, REG> PB9_SELECT_W<'a, REG>
276where
277 REG: crate::Writable + crate::RegisterSpec,
278 REG::Ux: From<u8>,
279{
280 #[doc = "`0`"]
281 #[inline(always)]
282 pub fn input(self) -> &'a mut crate::W<REG> {
283 self.variant(PB9_SELECT_A::INPUT)
284 }
285 #[doc = "`1`"]
286 #[inline(always)]
287 pub fn output(self) -> &'a mut crate::W<REG> {
288 self.variant(PB9_SELECT_A::OUTPUT)
289 }
290 #[doc = "`10`"]
291 #[inline(always)]
292 pub fn dmic_data2(self) -> &'a mut crate::W<REG> {
293 self.variant(PB9_SELECT_A::DMIC_DATA2)
294 }
295 #[doc = "`11`"]
296 #[inline(always)]
297 pub fn pwm6(self) -> &'a mut crate::W<REG> {
298 self.variant(PB9_SELECT_A::PWM6)
299 }
300 #[doc = "`100`"]
301 #[inline(always)]
302 pub fn twi2_sda(self) -> &'a mut crate::W<REG> {
303 self.variant(PB9_SELECT_A::TWI2_SDA)
304 }
305 #[doc = "`101`"]
306 #[inline(always)]
307 pub fn spi1_miso_dbi_sdi_dbi_te_dbi_dcx(self) -> &'a mut crate::W<REG> {
308 self.variant(PB9_SELECT_A::SPI1_MISO_DBI_SDI_DBI_TE_DBI_DCX)
309 }
310 #[doc = "`110`"]
311 #[inline(always)]
312 pub fn uart0_rx(self) -> &'a mut crate::W<REG> {
313 self.variant(PB9_SELECT_A::UART0_RX)
314 }
315 #[doc = "`111`"]
316 #[inline(always)]
317 pub fn uart1_rx(self) -> &'a mut crate::W<REG> {
318 self.variant(PB9_SELECT_A::UART1_RX)
319 }
320 #[doc = "`1110`"]
321 #[inline(always)]
322 pub fn pb_eint9(self) -> &'a mut crate::W<REG> {
323 self.variant(PB9_SELECT_A::PB_EINT9)
324 }
325 #[doc = "`1111`"]
326 #[inline(always)]
327 pub fn io_disable(self) -> &'a mut crate::W<REG> {
328 self.variant(PB9_SELECT_A::IO_DISABLE)
329 }
330}
331#[doc = "Field `pb10_select` reader - "]
332pub type PB10_SELECT_R = crate::FieldReader<PB10_SELECT_A>;
333#[doc = "\n\nValue on reset: 0"]
334#[derive(Clone, Copy, Debug, PartialEq, Eq)]
335#[repr(u8)]
336pub enum PB10_SELECT_A {
337 #[doc = "0: `0`"]
338 INPUT = 0,
339 #[doc = "1: `1`"]
340 OUTPUT = 1,
341 #[doc = "2: `10`"]
342 DMIC_DATA1 = 2,
343 #[doc = "3: `11`"]
344 PWM7 = 3,
345 #[doc = "4: `100`"]
346 TWI0_SCK = 4,
347 #[doc = "5: `101`"]
348 SPI1_MOSI_DBI_SDO = 5,
349 #[doc = "6: `110`"]
350 CLK_FANOUT0 = 6,
351 #[doc = "7: `111`"]
352 UART1_RTS = 7,
353 #[doc = "14: `1110`"]
354 PB_EINT10 = 14,
355 #[doc = "15: `1111`"]
356 IO_DISABLE = 15,
357}
358impl From<PB10_SELECT_A> for u8 {
359 #[inline(always)]
360 fn from(variant: PB10_SELECT_A) -> Self {
361 variant as _
362 }
363}
364impl crate::FieldSpec for PB10_SELECT_A {
365 type Ux = u8;
366}
367impl PB10_SELECT_R {
368 #[doc = "Get enumerated values variant"]
369 #[inline(always)]
370 pub const fn variant(&self) -> Option<PB10_SELECT_A> {
371 match self.bits {
372 0 => Some(PB10_SELECT_A::INPUT),
373 1 => Some(PB10_SELECT_A::OUTPUT),
374 2 => Some(PB10_SELECT_A::DMIC_DATA1),
375 3 => Some(PB10_SELECT_A::PWM7),
376 4 => Some(PB10_SELECT_A::TWI0_SCK),
377 5 => Some(PB10_SELECT_A::SPI1_MOSI_DBI_SDO),
378 6 => Some(PB10_SELECT_A::CLK_FANOUT0),
379 7 => Some(PB10_SELECT_A::UART1_RTS),
380 14 => Some(PB10_SELECT_A::PB_EINT10),
381 15 => Some(PB10_SELECT_A::IO_DISABLE),
382 _ => None,
383 }
384 }
385 #[doc = "`0`"]
386 #[inline(always)]
387 pub fn is_input(&self) -> bool {
388 *self == PB10_SELECT_A::INPUT
389 }
390 #[doc = "`1`"]
391 #[inline(always)]
392 pub fn is_output(&self) -> bool {
393 *self == PB10_SELECT_A::OUTPUT
394 }
395 #[doc = "`10`"]
396 #[inline(always)]
397 pub fn is_dmic_data1(&self) -> bool {
398 *self == PB10_SELECT_A::DMIC_DATA1
399 }
400 #[doc = "`11`"]
401 #[inline(always)]
402 pub fn is_pwm7(&self) -> bool {
403 *self == PB10_SELECT_A::PWM7
404 }
405 #[doc = "`100`"]
406 #[inline(always)]
407 pub fn is_twi0_sck(&self) -> bool {
408 *self == PB10_SELECT_A::TWI0_SCK
409 }
410 #[doc = "`101`"]
411 #[inline(always)]
412 pub fn is_spi1_mosi_dbi_sdo(&self) -> bool {
413 *self == PB10_SELECT_A::SPI1_MOSI_DBI_SDO
414 }
415 #[doc = "`110`"]
416 #[inline(always)]
417 pub fn is_clk_fanout0(&self) -> bool {
418 *self == PB10_SELECT_A::CLK_FANOUT0
419 }
420 #[doc = "`111`"]
421 #[inline(always)]
422 pub fn is_uart1_rts(&self) -> bool {
423 *self == PB10_SELECT_A::UART1_RTS
424 }
425 #[doc = "`1110`"]
426 #[inline(always)]
427 pub fn is_pb_eint10(&self) -> bool {
428 *self == PB10_SELECT_A::PB_EINT10
429 }
430 #[doc = "`1111`"]
431 #[inline(always)]
432 pub fn is_io_disable(&self) -> bool {
433 *self == PB10_SELECT_A::IO_DISABLE
434 }
435}
436#[doc = "Field `pb10_select` writer - "]
437pub type PB10_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PB10_SELECT_A>;
438impl<'a, REG> PB10_SELECT_W<'a, REG>
439where
440 REG: crate::Writable + crate::RegisterSpec,
441 REG::Ux: From<u8>,
442{
443 #[doc = "`0`"]
444 #[inline(always)]
445 pub fn input(self) -> &'a mut crate::W<REG> {
446 self.variant(PB10_SELECT_A::INPUT)
447 }
448 #[doc = "`1`"]
449 #[inline(always)]
450 pub fn output(self) -> &'a mut crate::W<REG> {
451 self.variant(PB10_SELECT_A::OUTPUT)
452 }
453 #[doc = "`10`"]
454 #[inline(always)]
455 pub fn dmic_data1(self) -> &'a mut crate::W<REG> {
456 self.variant(PB10_SELECT_A::DMIC_DATA1)
457 }
458 #[doc = "`11`"]
459 #[inline(always)]
460 pub fn pwm7(self) -> &'a mut crate::W<REG> {
461 self.variant(PB10_SELECT_A::PWM7)
462 }
463 #[doc = "`100`"]
464 #[inline(always)]
465 pub fn twi0_sck(self) -> &'a mut crate::W<REG> {
466 self.variant(PB10_SELECT_A::TWI0_SCK)
467 }
468 #[doc = "`101`"]
469 #[inline(always)]
470 pub fn spi1_mosi_dbi_sdo(self) -> &'a mut crate::W<REG> {
471 self.variant(PB10_SELECT_A::SPI1_MOSI_DBI_SDO)
472 }
473 #[doc = "`110`"]
474 #[inline(always)]
475 pub fn clk_fanout0(self) -> &'a mut crate::W<REG> {
476 self.variant(PB10_SELECT_A::CLK_FANOUT0)
477 }
478 #[doc = "`111`"]
479 #[inline(always)]
480 pub fn uart1_rts(self) -> &'a mut crate::W<REG> {
481 self.variant(PB10_SELECT_A::UART1_RTS)
482 }
483 #[doc = "`1110`"]
484 #[inline(always)]
485 pub fn pb_eint10(self) -> &'a mut crate::W<REG> {
486 self.variant(PB10_SELECT_A::PB_EINT10)
487 }
488 #[doc = "`1111`"]
489 #[inline(always)]
490 pub fn io_disable(self) -> &'a mut crate::W<REG> {
491 self.variant(PB10_SELECT_A::IO_DISABLE)
492 }
493}
494#[doc = "Field `pb11_select` reader - "]
495pub type PB11_SELECT_R = crate::FieldReader<PB11_SELECT_A>;
496#[doc = "\n\nValue on reset: 0"]
497#[derive(Clone, Copy, Debug, PartialEq, Eq)]
498#[repr(u8)]
499pub enum PB11_SELECT_A {
500 #[doc = "0: `0`"]
501 INPUT = 0,
502 #[doc = "1: `1`"]
503 OUTPUT = 1,
504 #[doc = "2: `10`"]
505 DMIC_DATA0 = 2,
506 #[doc = "3: `11`"]
507 PWM2 = 3,
508 #[doc = "4: `100`"]
509 TWI0_SDA = 4,
510 #[doc = "5: `101`"]
511 SPI1_CLK_DBI_SCLK = 5,
512 #[doc = "6: `110`"]
513 CLK_FANOUT1 = 6,
514 #[doc = "7: `111`"]
515 UART1_CTS = 7,
516 #[doc = "14: `1110`"]
517 PB_EINT11 = 14,
518 #[doc = "15: `1111`"]
519 IO_DISABLE = 15,
520}
521impl From<PB11_SELECT_A> for u8 {
522 #[inline(always)]
523 fn from(variant: PB11_SELECT_A) -> Self {
524 variant as _
525 }
526}
527impl crate::FieldSpec for PB11_SELECT_A {
528 type Ux = u8;
529}
530impl PB11_SELECT_R {
531 #[doc = "Get enumerated values variant"]
532 #[inline(always)]
533 pub const fn variant(&self) -> Option<PB11_SELECT_A> {
534 match self.bits {
535 0 => Some(PB11_SELECT_A::INPUT),
536 1 => Some(PB11_SELECT_A::OUTPUT),
537 2 => Some(PB11_SELECT_A::DMIC_DATA0),
538 3 => Some(PB11_SELECT_A::PWM2),
539 4 => Some(PB11_SELECT_A::TWI0_SDA),
540 5 => Some(PB11_SELECT_A::SPI1_CLK_DBI_SCLK),
541 6 => Some(PB11_SELECT_A::CLK_FANOUT1),
542 7 => Some(PB11_SELECT_A::UART1_CTS),
543 14 => Some(PB11_SELECT_A::PB_EINT11),
544 15 => Some(PB11_SELECT_A::IO_DISABLE),
545 _ => None,
546 }
547 }
548 #[doc = "`0`"]
549 #[inline(always)]
550 pub fn is_input(&self) -> bool {
551 *self == PB11_SELECT_A::INPUT
552 }
553 #[doc = "`1`"]
554 #[inline(always)]
555 pub fn is_output(&self) -> bool {
556 *self == PB11_SELECT_A::OUTPUT
557 }
558 #[doc = "`10`"]
559 #[inline(always)]
560 pub fn is_dmic_data0(&self) -> bool {
561 *self == PB11_SELECT_A::DMIC_DATA0
562 }
563 #[doc = "`11`"]
564 #[inline(always)]
565 pub fn is_pwm2(&self) -> bool {
566 *self == PB11_SELECT_A::PWM2
567 }
568 #[doc = "`100`"]
569 #[inline(always)]
570 pub fn is_twi0_sda(&self) -> bool {
571 *self == PB11_SELECT_A::TWI0_SDA
572 }
573 #[doc = "`101`"]
574 #[inline(always)]
575 pub fn is_spi1_clk_dbi_sclk(&self) -> bool {
576 *self == PB11_SELECT_A::SPI1_CLK_DBI_SCLK
577 }
578 #[doc = "`110`"]
579 #[inline(always)]
580 pub fn is_clk_fanout1(&self) -> bool {
581 *self == PB11_SELECT_A::CLK_FANOUT1
582 }
583 #[doc = "`111`"]
584 #[inline(always)]
585 pub fn is_uart1_cts(&self) -> bool {
586 *self == PB11_SELECT_A::UART1_CTS
587 }
588 #[doc = "`1110`"]
589 #[inline(always)]
590 pub fn is_pb_eint11(&self) -> bool {
591 *self == PB11_SELECT_A::PB_EINT11
592 }
593 #[doc = "`1111`"]
594 #[inline(always)]
595 pub fn is_io_disable(&self) -> bool {
596 *self == PB11_SELECT_A::IO_DISABLE
597 }
598}
599#[doc = "Field `pb11_select` writer - "]
600pub type PB11_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PB11_SELECT_A>;
601impl<'a, REG> PB11_SELECT_W<'a, REG>
602where
603 REG: crate::Writable + crate::RegisterSpec,
604 REG::Ux: From<u8>,
605{
606 #[doc = "`0`"]
607 #[inline(always)]
608 pub fn input(self) -> &'a mut crate::W<REG> {
609 self.variant(PB11_SELECT_A::INPUT)
610 }
611 #[doc = "`1`"]
612 #[inline(always)]
613 pub fn output(self) -> &'a mut crate::W<REG> {
614 self.variant(PB11_SELECT_A::OUTPUT)
615 }
616 #[doc = "`10`"]
617 #[inline(always)]
618 pub fn dmic_data0(self) -> &'a mut crate::W<REG> {
619 self.variant(PB11_SELECT_A::DMIC_DATA0)
620 }
621 #[doc = "`11`"]
622 #[inline(always)]
623 pub fn pwm2(self) -> &'a mut crate::W<REG> {
624 self.variant(PB11_SELECT_A::PWM2)
625 }
626 #[doc = "`100`"]
627 #[inline(always)]
628 pub fn twi0_sda(self) -> &'a mut crate::W<REG> {
629 self.variant(PB11_SELECT_A::TWI0_SDA)
630 }
631 #[doc = "`101`"]
632 #[inline(always)]
633 pub fn spi1_clk_dbi_sclk(self) -> &'a mut crate::W<REG> {
634 self.variant(PB11_SELECT_A::SPI1_CLK_DBI_SCLK)
635 }
636 #[doc = "`110`"]
637 #[inline(always)]
638 pub fn clk_fanout1(self) -> &'a mut crate::W<REG> {
639 self.variant(PB11_SELECT_A::CLK_FANOUT1)
640 }
641 #[doc = "`111`"]
642 #[inline(always)]
643 pub fn uart1_cts(self) -> &'a mut crate::W<REG> {
644 self.variant(PB11_SELECT_A::UART1_CTS)
645 }
646 #[doc = "`1110`"]
647 #[inline(always)]
648 pub fn pb_eint11(self) -> &'a mut crate::W<REG> {
649 self.variant(PB11_SELECT_A::PB_EINT11)
650 }
651 #[doc = "`1111`"]
652 #[inline(always)]
653 pub fn io_disable(self) -> &'a mut crate::W<REG> {
654 self.variant(PB11_SELECT_A::IO_DISABLE)
655 }
656}
657#[doc = "Field `pb12_select` reader - "]
658pub type PB12_SELECT_R = crate::FieldReader<PB12_SELECT_A>;
659#[doc = "\n\nValue on reset: 0"]
660#[derive(Clone, Copy, Debug, PartialEq, Eq)]
661#[repr(u8)]
662pub enum PB12_SELECT_A {
663 #[doc = "0: `0`"]
664 INPUT = 0,
665 #[doc = "1: `1`"]
666 OUTPUT = 1,
667 #[doc = "2: `10`"]
668 DMIC_CLK = 2,
669 #[doc = "3: `11`"]
670 PWM0 = 3,
671 #[doc = "4: `100`"]
672 OWA_IN = 4,
673 #[doc = "5: `101`"]
674 SPI1_CS_DBI_CSX = 5,
675 #[doc = "6: `110`"]
676 CLK_FANOUT2 = 6,
677 #[doc = "7: `111`"]
678 IR_RX = 7,
679 #[doc = "14: `1110`"]
680 PB_EINT12 = 14,
681 #[doc = "15: `1111`"]
682 IO_DISABLE = 15,
683}
684impl From<PB12_SELECT_A> for u8 {
685 #[inline(always)]
686 fn from(variant: PB12_SELECT_A) -> Self {
687 variant as _
688 }
689}
690impl crate::FieldSpec for PB12_SELECT_A {
691 type Ux = u8;
692}
693impl PB12_SELECT_R {
694 #[doc = "Get enumerated values variant"]
695 #[inline(always)]
696 pub const fn variant(&self) -> Option<PB12_SELECT_A> {
697 match self.bits {
698 0 => Some(PB12_SELECT_A::INPUT),
699 1 => Some(PB12_SELECT_A::OUTPUT),
700 2 => Some(PB12_SELECT_A::DMIC_CLK),
701 3 => Some(PB12_SELECT_A::PWM0),
702 4 => Some(PB12_SELECT_A::OWA_IN),
703 5 => Some(PB12_SELECT_A::SPI1_CS_DBI_CSX),
704 6 => Some(PB12_SELECT_A::CLK_FANOUT2),
705 7 => Some(PB12_SELECT_A::IR_RX),
706 14 => Some(PB12_SELECT_A::PB_EINT12),
707 15 => Some(PB12_SELECT_A::IO_DISABLE),
708 _ => None,
709 }
710 }
711 #[doc = "`0`"]
712 #[inline(always)]
713 pub fn is_input(&self) -> bool {
714 *self == PB12_SELECT_A::INPUT
715 }
716 #[doc = "`1`"]
717 #[inline(always)]
718 pub fn is_output(&self) -> bool {
719 *self == PB12_SELECT_A::OUTPUT
720 }
721 #[doc = "`10`"]
722 #[inline(always)]
723 pub fn is_dmic_clk(&self) -> bool {
724 *self == PB12_SELECT_A::DMIC_CLK
725 }
726 #[doc = "`11`"]
727 #[inline(always)]
728 pub fn is_pwm0(&self) -> bool {
729 *self == PB12_SELECT_A::PWM0
730 }
731 #[doc = "`100`"]
732 #[inline(always)]
733 pub fn is_owa_in(&self) -> bool {
734 *self == PB12_SELECT_A::OWA_IN
735 }
736 #[doc = "`101`"]
737 #[inline(always)]
738 pub fn is_spi1_cs_dbi_csx(&self) -> bool {
739 *self == PB12_SELECT_A::SPI1_CS_DBI_CSX
740 }
741 #[doc = "`110`"]
742 #[inline(always)]
743 pub fn is_clk_fanout2(&self) -> bool {
744 *self == PB12_SELECT_A::CLK_FANOUT2
745 }
746 #[doc = "`111`"]
747 #[inline(always)]
748 pub fn is_ir_rx(&self) -> bool {
749 *self == PB12_SELECT_A::IR_RX
750 }
751 #[doc = "`1110`"]
752 #[inline(always)]
753 pub fn is_pb_eint12(&self) -> bool {
754 *self == PB12_SELECT_A::PB_EINT12
755 }
756 #[doc = "`1111`"]
757 #[inline(always)]
758 pub fn is_io_disable(&self) -> bool {
759 *self == PB12_SELECT_A::IO_DISABLE
760 }
761}
762#[doc = "Field `pb12_select` writer - "]
763pub type PB12_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PB12_SELECT_A>;
764impl<'a, REG> PB12_SELECT_W<'a, REG>
765where
766 REG: crate::Writable + crate::RegisterSpec,
767 REG::Ux: From<u8>,
768{
769 #[doc = "`0`"]
770 #[inline(always)]
771 pub fn input(self) -> &'a mut crate::W<REG> {
772 self.variant(PB12_SELECT_A::INPUT)
773 }
774 #[doc = "`1`"]
775 #[inline(always)]
776 pub fn output(self) -> &'a mut crate::W<REG> {
777 self.variant(PB12_SELECT_A::OUTPUT)
778 }
779 #[doc = "`10`"]
780 #[inline(always)]
781 pub fn dmic_clk(self) -> &'a mut crate::W<REG> {
782 self.variant(PB12_SELECT_A::DMIC_CLK)
783 }
784 #[doc = "`11`"]
785 #[inline(always)]
786 pub fn pwm0(self) -> &'a mut crate::W<REG> {
787 self.variant(PB12_SELECT_A::PWM0)
788 }
789 #[doc = "`100`"]
790 #[inline(always)]
791 pub fn owa_in(self) -> &'a mut crate::W<REG> {
792 self.variant(PB12_SELECT_A::OWA_IN)
793 }
794 #[doc = "`101`"]
795 #[inline(always)]
796 pub fn spi1_cs_dbi_csx(self) -> &'a mut crate::W<REG> {
797 self.variant(PB12_SELECT_A::SPI1_CS_DBI_CSX)
798 }
799 #[doc = "`110`"]
800 #[inline(always)]
801 pub fn clk_fanout2(self) -> &'a mut crate::W<REG> {
802 self.variant(PB12_SELECT_A::CLK_FANOUT2)
803 }
804 #[doc = "`111`"]
805 #[inline(always)]
806 pub fn ir_rx(self) -> &'a mut crate::W<REG> {
807 self.variant(PB12_SELECT_A::IR_RX)
808 }
809 #[doc = "`1110`"]
810 #[inline(always)]
811 pub fn pb_eint12(self) -> &'a mut crate::W<REG> {
812 self.variant(PB12_SELECT_A::PB_EINT12)
813 }
814 #[doc = "`1111`"]
815 #[inline(always)]
816 pub fn io_disable(self) -> &'a mut crate::W<REG> {
817 self.variant(PB12_SELECT_A::IO_DISABLE)
818 }
819}
820impl R {
821 #[doc = "Bits 0:3"]
822 #[inline(always)]
823 pub fn pb8_select(&self) -> PB8_SELECT_R {
824 PB8_SELECT_R::new((self.bits & 0x0f) as u8)
825 }
826 #[doc = "Bits 4:7"]
827 #[inline(always)]
828 pub fn pb9_select(&self) -> PB9_SELECT_R {
829 PB9_SELECT_R::new(((self.bits >> 4) & 0x0f) as u8)
830 }
831 #[doc = "Bits 8:11"]
832 #[inline(always)]
833 pub fn pb10_select(&self) -> PB10_SELECT_R {
834 PB10_SELECT_R::new(((self.bits >> 8) & 0x0f) as u8)
835 }
836 #[doc = "Bits 12:15"]
837 #[inline(always)]
838 pub fn pb11_select(&self) -> PB11_SELECT_R {
839 PB11_SELECT_R::new(((self.bits >> 12) & 0x0f) as u8)
840 }
841 #[doc = "Bits 16:19"]
842 #[inline(always)]
843 pub fn pb12_select(&self) -> PB12_SELECT_R {
844 PB12_SELECT_R::new(((self.bits >> 16) & 0x0f) as u8)
845 }
846}
847impl W {
848 #[doc = "Bits 0:3"]
849 #[inline(always)]
850 #[must_use]
851 pub fn pb8_select(&mut self) -> PB8_SELECT_W<PB_CFG1_SPEC> {
852 PB8_SELECT_W::new(self, 0)
853 }
854 #[doc = "Bits 4:7"]
855 #[inline(always)]
856 #[must_use]
857 pub fn pb9_select(&mut self) -> PB9_SELECT_W<PB_CFG1_SPEC> {
858 PB9_SELECT_W::new(self, 4)
859 }
860 #[doc = "Bits 8:11"]
861 #[inline(always)]
862 #[must_use]
863 pub fn pb10_select(&mut self) -> PB10_SELECT_W<PB_CFG1_SPEC> {
864 PB10_SELECT_W::new(self, 8)
865 }
866 #[doc = "Bits 12:15"]
867 #[inline(always)]
868 #[must_use]
869 pub fn pb11_select(&mut self) -> PB11_SELECT_W<PB_CFG1_SPEC> {
870 PB11_SELECT_W::new(self, 12)
871 }
872 #[doc = "Bits 16:19"]
873 #[inline(always)]
874 #[must_use]
875 pub fn pb12_select(&mut self) -> PB12_SELECT_W<PB_CFG1_SPEC> {
876 PB12_SELECT_W::new(self, 16)
877 }
878 #[doc = r" Writes raw bits to the register."]
879 #[doc = r""]
880 #[doc = r" # Safety"]
881 #[doc = r""]
882 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
883 #[inline(always)]
884 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
885 self.bits = bits;
886 self
887 }
888}
889#[doc = "PB Configure Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pb_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pb_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
890pub struct PB_CFG1_SPEC;
891impl crate::RegisterSpec for PB_CFG1_SPEC {
892 type Ux = u32;
893}
894#[doc = "`read()` method returns [`pb_cfg1::R`](R) reader structure"]
895impl crate::Readable for PB_CFG1_SPEC {}
896#[doc = "`write(|w| ..)` method takes [`pb_cfg1::W`](W) writer structure"]
897impl crate::Writable for PB_CFG1_SPEC {
898 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
899 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
900}
901#[doc = "`reset()` method sets pb_cfg1 to value 0"]
902impl crate::Resettable for PB_CFG1_SPEC {
903 const RESET_VALUE: Self::Ux = 0;
904}