d1_pac/gpadc/
gp_sr_con.rs

1#[doc = "Register `gp_sr_con` reader"]
2pub type R = crate::R<GP_SR_CON_SPEC>;
3#[doc = "Register `gp_sr_con` writer"]
4pub type W = crate::W<GP_SR_CON_SPEC>;
5#[doc = "Field `tacq` reader - ADC acquire time\n\n(n+1)/CLK_IN\n\nDefault value: 2 us"]
6pub type TACQ_R = crate::FieldReader<u16>;
7#[doc = "Field `tacq` writer - ADC acquire time\n\n(n+1)/CLK_IN\n\nDefault value: 2 us"]
8pub type TACQ_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `fs_div` reader - ADC sample frequency divider\n\nCLK_IN/(n+1)\n\nDefault value: 50K"]
10pub type FS_DIV_R = crate::FieldReader<u16>;
11#[doc = "Field `fs_div` writer - ADC sample frequency divider\n\nCLK_IN/(n+1)\n\nDefault value: 50K"]
12pub type FS_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13impl R {
14    #[doc = "Bits 0:15 - ADC acquire time\n\n(n+1)/CLK_IN\n\nDefault value: 2 us"]
15    #[inline(always)]
16    pub fn tacq(&self) -> TACQ_R {
17        TACQ_R::new((self.bits & 0xffff) as u16)
18    }
19    #[doc = "Bits 16:31 - ADC sample frequency divider\n\nCLK_IN/(n+1)\n\nDefault value: 50K"]
20    #[inline(always)]
21    pub fn fs_div(&self) -> FS_DIV_R {
22        FS_DIV_R::new(((self.bits >> 16) & 0xffff) as u16)
23    }
24}
25impl W {
26    #[doc = "Bits 0:15 - ADC acquire time\n\n(n+1)/CLK_IN\n\nDefault value: 2 us"]
27    #[inline(always)]
28    #[must_use]
29    pub fn tacq(&mut self) -> TACQ_W<GP_SR_CON_SPEC> {
30        TACQ_W::new(self, 0)
31    }
32    #[doc = "Bits 16:31 - ADC sample frequency divider\n\nCLK_IN/(n+1)\n\nDefault value: 50K"]
33    #[inline(always)]
34    #[must_use]
35    pub fn fs_div(&mut self) -> FS_DIV_W<GP_SR_CON_SPEC> {
36        FS_DIV_W::new(self, 16)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "GPADC Sample Rate Configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gp_sr_con::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gp_sr_con::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
50pub struct GP_SR_CON_SPEC;
51impl crate::RegisterSpec for GP_SR_CON_SPEC {
52    type Ux = u32;
53}
54#[doc = "`read()` method returns [`gp_sr_con::R`](R) reader structure"]
55impl crate::Readable for GP_SR_CON_SPEC {}
56#[doc = "`write(|w| ..)` method takes [`gp_sr_con::W`](W) writer structure"]
57impl crate::Writable for GP_SR_CON_SPEC {
58    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
59    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
60}
61#[doc = "`reset()` method sets gp_sr_con to value 0x01df_002f"]
62impl crate::Resettable for GP_SR_CON_SPEC {
63    const RESET_VALUE: Self::Ux = 0x01df_002f;
64}
d1_pac/gpadc/gp_sr_con.rs

d1_pac/gpadc/
gp_sr_con.rs
