1#[doc = "Register `gp_cs_en` reader"]
2pub type R = crate::R<GP_CS_EN_SPEC>;
3#[doc = "Register `gp_cs_en` writer"]
4pub type W = crate::W<GP_CS_EN_SPEC>;
5#[doc = "Field `adc_ch_select[0-1]` reader - Analog Input Channel Select"]
6pub type ADC_CH_SELECT_R = crate::BitReader<ADC_CH_SELECT_A>;
7#[doc = "Analog Input Channel Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum ADC_CH_SELECT_A {
10 #[doc = "0: Disable"]
11 DISABLE = 0,
12 #[doc = "1: Enable"]
13 ENABLE = 1,
14}
15impl From<ADC_CH_SELECT_A> for bool {
16 #[inline(always)]
17 fn from(variant: ADC_CH_SELECT_A) -> Self {
18 variant as u8 != 0
19 }
20}
21impl ADC_CH_SELECT_R {
22 #[doc = "Get enumerated values variant"]
23 #[inline(always)]
24 pub const fn variant(&self) -> ADC_CH_SELECT_A {
25 match self.bits {
26 false => ADC_CH_SELECT_A::DISABLE,
27 true => ADC_CH_SELECT_A::ENABLE,
28 }
29 }
30 #[doc = "Disable"]
31 #[inline(always)]
32 pub fn is_disable(&self) -> bool {
33 *self == ADC_CH_SELECT_A::DISABLE
34 }
35 #[doc = "Enable"]
36 #[inline(always)]
37 pub fn is_enable(&self) -> bool {
38 *self == ADC_CH_SELECT_A::ENABLE
39 }
40}
41#[doc = "Field `adc_ch_select[0-1]` writer - Analog Input Channel Select"]
42pub type ADC_CH_SELECT_W<'a, REG> = crate::BitWriter<'a, REG, ADC_CH_SELECT_A>;
43impl<'a, REG> ADC_CH_SELECT_W<'a, REG>
44where
45 REG: crate::Writable + crate::RegisterSpec,
46{
47 #[doc = "Disable"]
48 #[inline(always)]
49 pub fn disable(self) -> &'a mut crate::W<REG> {
50 self.variant(ADC_CH_SELECT_A::DISABLE)
51 }
52 #[doc = "Enable"]
53 #[inline(always)]
54 pub fn enable(self) -> &'a mut crate::W<REG> {
55 self.variant(ADC_CH_SELECT_A::ENABLE)
56 }
57}
58#[doc = "Field `adc_ch_cmp_en[0-1]` reader - Channel Compare Enable"]
59pub type ADC_CH_CMP_EN_R = crate::BitReader<ADC_CH_CMP_EN_A>;
60#[doc = "Channel Compare Enable\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum ADC_CH_CMP_EN_A {
63 #[doc = "0: Disable"]
64 DISABLE = 0,
65 #[doc = "1: Enable"]
66 ENABLE = 1,
67}
68impl From<ADC_CH_CMP_EN_A> for bool {
69 #[inline(always)]
70 fn from(variant: ADC_CH_CMP_EN_A) -> Self {
71 variant as u8 != 0
72 }
73}
74impl ADC_CH_CMP_EN_R {
75 #[doc = "Get enumerated values variant"]
76 #[inline(always)]
77 pub const fn variant(&self) -> ADC_CH_CMP_EN_A {
78 match self.bits {
79 false => ADC_CH_CMP_EN_A::DISABLE,
80 true => ADC_CH_CMP_EN_A::ENABLE,
81 }
82 }
83 #[doc = "Disable"]
84 #[inline(always)]
85 pub fn is_disable(&self) -> bool {
86 *self == ADC_CH_CMP_EN_A::DISABLE
87 }
88 #[doc = "Enable"]
89 #[inline(always)]
90 pub fn is_enable(&self) -> bool {
91 *self == ADC_CH_CMP_EN_A::ENABLE
92 }
93}
94#[doc = "Field `adc_ch_cmp_en[0-1]` writer - Channel Compare Enable"]
95pub type ADC_CH_CMP_EN_W<'a, REG> = crate::BitWriter<'a, REG, ADC_CH_CMP_EN_A>;
96impl<'a, REG> ADC_CH_CMP_EN_W<'a, REG>
97where
98 REG: crate::Writable + crate::RegisterSpec,
99{
100 #[doc = "Disable"]
101 #[inline(always)]
102 pub fn disable(self) -> &'a mut crate::W<REG> {
103 self.variant(ADC_CH_CMP_EN_A::DISABLE)
104 }
105 #[doc = "Enable"]
106 #[inline(always)]
107 pub fn enable(self) -> &'a mut crate::W<REG> {
108 self.variant(ADC_CH_CMP_EN_A::ENABLE)
109 }
110}
111impl R {
112 #[doc = "Analog Input Channel Select\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `adc_ch0_select` field"]
113 #[inline(always)]
114 pub fn adc_ch_select(&self, n: u8) -> ADC_CH_SELECT_R {
115 #[allow(clippy::no_effect)]
116 [(); 2][n as usize];
117 ADC_CH_SELECT_R::new(((self.bits >> n) & 1) != 0)
118 }
119 #[doc = "Bit 0 - Analog Input Channel Select"]
120 #[inline(always)]
121 pub fn adc_ch0_select(&self) -> ADC_CH_SELECT_R {
122 ADC_CH_SELECT_R::new((self.bits & 1) != 0)
123 }
124 #[doc = "Bit 1 - Analog Input Channel Select"]
125 #[inline(always)]
126 pub fn adc_ch1_select(&self) -> ADC_CH_SELECT_R {
127 ADC_CH_SELECT_R::new(((self.bits >> 1) & 1) != 0)
128 }
129 #[doc = "Channel Compare Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `adc_ch0_cmp_en` field"]
130 #[inline(always)]
131 pub fn adc_ch_cmp_en(&self, n: u8) -> ADC_CH_CMP_EN_R {
132 #[allow(clippy::no_effect)]
133 [(); 2][n as usize];
134 ADC_CH_CMP_EN_R::new(((self.bits >> (n + 16)) & 1) != 0)
135 }
136 #[doc = "Bit 16 - Channel Compare Enable"]
137 #[inline(always)]
138 pub fn adc_ch0_cmp_en(&self) -> ADC_CH_CMP_EN_R {
139 ADC_CH_CMP_EN_R::new(((self.bits >> 16) & 1) != 0)
140 }
141 #[doc = "Bit 17 - Channel Compare Enable"]
142 #[inline(always)]
143 pub fn adc_ch1_cmp_en(&self) -> ADC_CH_CMP_EN_R {
144 ADC_CH_CMP_EN_R::new(((self.bits >> 17) & 1) != 0)
145 }
146}
147impl W {
148 #[doc = "Analog Input Channel Select\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `adc_ch0_select` field"]
149 #[inline(always)]
150 #[must_use]
151 pub fn adc_ch_select(&mut self, n: u8) -> ADC_CH_SELECT_W<GP_CS_EN_SPEC> {
152 #[allow(clippy::no_effect)]
153 [(); 2][n as usize];
154 ADC_CH_SELECT_W::new(self, n)
155 }
156 #[doc = "Bit 0 - Analog Input Channel Select"]
157 #[inline(always)]
158 #[must_use]
159 pub fn adc_ch0_select(&mut self) -> ADC_CH_SELECT_W<GP_CS_EN_SPEC> {
160 ADC_CH_SELECT_W::new(self, 0)
161 }
162 #[doc = "Bit 1 - Analog Input Channel Select"]
163 #[inline(always)]
164 #[must_use]
165 pub fn adc_ch1_select(&mut self) -> ADC_CH_SELECT_W<GP_CS_EN_SPEC> {
166 ADC_CH_SELECT_W::new(self, 1)
167 }
168 #[doc = "Channel Compare Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `adc_ch0_cmp_en` field"]
169 #[inline(always)]
170 #[must_use]
171 pub fn adc_ch_cmp_en(&mut self, n: u8) -> ADC_CH_CMP_EN_W<GP_CS_EN_SPEC> {
172 #[allow(clippy::no_effect)]
173 [(); 2][n as usize];
174 ADC_CH_CMP_EN_W::new(self, n + 16)
175 }
176 #[doc = "Bit 16 - Channel Compare Enable"]
177 #[inline(always)]
178 #[must_use]
179 pub fn adc_ch0_cmp_en(&mut self) -> ADC_CH_CMP_EN_W<GP_CS_EN_SPEC> {
180 ADC_CH_CMP_EN_W::new(self, 16)
181 }
182 #[doc = "Bit 17 - Channel Compare Enable"]
183 #[inline(always)]
184 #[must_use]
185 pub fn adc_ch1_cmp_en(&mut self) -> ADC_CH_CMP_EN_W<GP_CS_EN_SPEC> {
186 ADC_CH_CMP_EN_W::new(self, 17)
187 }
188 #[doc = r" Writes raw bits to the register."]
189 #[doc = r""]
190 #[doc = r" # Safety"]
191 #[doc = r""]
192 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
193 #[inline(always)]
194 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
195 self.bits = bits;
196 self
197 }
198}
199#[doc = "GPADC Compare and Select Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gp_cs_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gp_cs_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
200pub struct GP_CS_EN_SPEC;
201impl crate::RegisterSpec for GP_CS_EN_SPEC {
202 type Ux = u32;
203}
204#[doc = "`read()` method returns [`gp_cs_en::R`](R) reader structure"]
205impl crate::Readable for GP_CS_EN_SPEC {}
206#[doc = "`write(|w| ..)` method takes [`gp_cs_en::W`](W) writer structure"]
207impl crate::Writable for GP_CS_EN_SPEC {
208 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
209 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
210}
211#[doc = "`reset()` method sets gp_cs_en to value 0"]
212impl crate::Resettable for GP_CS_EN_SPEC {
213 const RESET_VALUE: Self::Ux = 0;
214}