d1_pac/emac/
emac_tx_ctl1.rs

1#[doc = "Register `emac_tx_ctl1` reader"]
2pub type R = crate::R<EMAC_TX_CTL1_SPEC>;
3#[doc = "Register `emac_tx_ctl1` writer"]
4pub type W = crate::W<EMAC_TX_CTL1_SPEC>;
5#[doc = "Field `flush_tx_fifo` reader - Flush the data in the TX FIFO"]
6pub type FLUSH_TX_FIFO_R = crate::BitReader<FLUSH_TX_FIFO_A>;
7#[doc = "Flush the data in the TX FIFO\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum FLUSH_TX_FIFO_A {
10    #[doc = "0: `0`"]
11    ENABLE = 0,
12    #[doc = "1: `1`"]
13    DISABLE = 1,
14}
15impl From<FLUSH_TX_FIFO_A> for bool {
16    #[inline(always)]
17    fn from(variant: FLUSH_TX_FIFO_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl FLUSH_TX_FIFO_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> FLUSH_TX_FIFO_A {
25        match self.bits {
26            false => FLUSH_TX_FIFO_A::ENABLE,
27            true => FLUSH_TX_FIFO_A::DISABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_enable(&self) -> bool {
33        *self == FLUSH_TX_FIFO_A::ENABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_disable(&self) -> bool {
38        *self == FLUSH_TX_FIFO_A::DISABLE
39    }
40}
41#[doc = "Field `flush_tx_fifo` writer - Flush the data in the TX FIFO"]
42pub type FLUSH_TX_FIFO_W<'a, REG> = crate::BitWriter<'a, REG, FLUSH_TX_FIFO_A>;
43impl<'a, REG> FLUSH_TX_FIFO_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn enable(self) -> &'a mut crate::W<REG> {
50        self.variant(FLUSH_TX_FIFO_A::ENABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn disable(self) -> &'a mut crate::W<REG> {
55        self.variant(FLUSH_TX_FIFO_A::DISABLE)
56    }
57}
58#[doc = "Field `tx_md` reader - Transmission Mode"]
59pub type TX_MD_R = crate::BitReader<TX_MD_A>;
60#[doc = "Transmission Mode\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum TX_MD_A {
63    #[doc = "0: `0`"]
64    GREATER_THAN_TH = 0,
65    #[doc = "1: `1`"]
66    LOCATE_FULL_FRAME = 1,
67}
68impl From<TX_MD_A> for bool {
69    #[inline(always)]
70    fn from(variant: TX_MD_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl TX_MD_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> TX_MD_A {
78        match self.bits {
79            false => TX_MD_A::GREATER_THAN_TH,
80            true => TX_MD_A::LOCATE_FULL_FRAME,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_greater_than_th(&self) -> bool {
86        *self == TX_MD_A::GREATER_THAN_TH
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_locate_full_frame(&self) -> bool {
91        *self == TX_MD_A::LOCATE_FULL_FRAME
92    }
93}
94#[doc = "Field `tx_md` writer - Transmission Mode"]
95pub type TX_MD_W<'a, REG> = crate::BitWriter<'a, REG, TX_MD_A>;
96impl<'a, REG> TX_MD_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn greater_than_th(self) -> &'a mut crate::W<REG> {
103        self.variant(TX_MD_A::GREATER_THAN_TH)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn locate_full_frame(self) -> &'a mut crate::W<REG> {
108        self.variant(TX_MD_A::LOCATE_FULL_FRAME)
109    }
110}
111#[doc = "Field `tx_th` reader - Threshold value of TX DMA FIFO"]
112pub type TX_TH_R = crate::FieldReader<TX_TH_A>;
113#[doc = "Threshold value of TX DMA FIFO\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115#[repr(u8)]
116pub enum TX_TH_A {
117    #[doc = "0: `0`"]
118    T64 = 0,
119    #[doc = "1: `1`"]
120    T128 = 1,
121    #[doc = "2: `10`"]
122    T192 = 2,
123    #[doc = "3: `11`"]
124    T256 = 3,
125}
126impl From<TX_TH_A> for u8 {
127    #[inline(always)]
128    fn from(variant: TX_TH_A) -> Self {
129        variant as _
130    }
131}
132impl crate::FieldSpec for TX_TH_A {
133    type Ux = u8;
134}
135impl TX_TH_R {
136    #[doc = "Get enumerated values variant"]
137    #[inline(always)]
138    pub const fn variant(&self) -> Option<TX_TH_A> {
139        match self.bits {
140            0 => Some(TX_TH_A::T64),
141            1 => Some(TX_TH_A::T128),
142            2 => Some(TX_TH_A::T192),
143            3 => Some(TX_TH_A::T256),
144            _ => None,
145        }
146    }
147    #[doc = "`0`"]
148    #[inline(always)]
149    pub fn is_t64(&self) -> bool {
150        *self == TX_TH_A::T64
151    }
152    #[doc = "`1`"]
153    #[inline(always)]
154    pub fn is_t128(&self) -> bool {
155        *self == TX_TH_A::T128
156    }
157    #[doc = "`10`"]
158    #[inline(always)]
159    pub fn is_t192(&self) -> bool {
160        *self == TX_TH_A::T192
161    }
162    #[doc = "`11`"]
163    #[inline(always)]
164    pub fn is_t256(&self) -> bool {
165        *self == TX_TH_A::T256
166    }
167}
168#[doc = "Field `tx_th` writer - Threshold value of TX DMA FIFO"]
169pub type TX_TH_W<'a, REG> = crate::FieldWriter<'a, REG, 3, TX_TH_A>;
170impl<'a, REG> TX_TH_W<'a, REG>
171where
172    REG: crate::Writable + crate::RegisterSpec,
173    REG::Ux: From<u8>,
174{
175    #[doc = "`0`"]
176    #[inline(always)]
177    pub fn t64(self) -> &'a mut crate::W<REG> {
178        self.variant(TX_TH_A::T64)
179    }
180    #[doc = "`1`"]
181    #[inline(always)]
182    pub fn t128(self) -> &'a mut crate::W<REG> {
183        self.variant(TX_TH_A::T128)
184    }
185    #[doc = "`10`"]
186    #[inline(always)]
187    pub fn t192(self) -> &'a mut crate::W<REG> {
188        self.variant(TX_TH_A::T192)
189    }
190    #[doc = "`11`"]
191    #[inline(always)]
192    pub fn t256(self) -> &'a mut crate::W<REG> {
193        self.variant(TX_TH_A::T256)
194    }
195}
196#[doc = "Field `tx_dma_en` reader - Transmit DMA Enable"]
197pub type TX_DMA_EN_R = crate::BitReader<TX_DMA_EN_A>;
198#[doc = "Transmit DMA Enable\n\nValue on reset: 0"]
199#[derive(Clone, Copy, Debug, PartialEq, Eq)]
200pub enum TX_DMA_EN_A {
201    #[doc = "0: `0`"]
202    STOP = 0,
203    #[doc = "1: `1`"]
204    START = 1,
205}
206impl From<TX_DMA_EN_A> for bool {
207    #[inline(always)]
208    fn from(variant: TX_DMA_EN_A) -> Self {
209        variant as u8 != 0
210    }
211}
212impl TX_DMA_EN_R {
213    #[doc = "Get enumerated values variant"]
214    #[inline(always)]
215    pub const fn variant(&self) -> TX_DMA_EN_A {
216        match self.bits {
217            false => TX_DMA_EN_A::STOP,
218            true => TX_DMA_EN_A::START,
219        }
220    }
221    #[doc = "`0`"]
222    #[inline(always)]
223    pub fn is_stop(&self) -> bool {
224        *self == TX_DMA_EN_A::STOP
225    }
226    #[doc = "`1`"]
227    #[inline(always)]
228    pub fn is_start(&self) -> bool {
229        *self == TX_DMA_EN_A::START
230    }
231}
232#[doc = "Field `tx_dma_en` writer - Transmit DMA Enable"]
233pub type TX_DMA_EN_W<'a, REG> = crate::BitWriter<'a, REG, TX_DMA_EN_A>;
234impl<'a, REG> TX_DMA_EN_W<'a, REG>
235where
236    REG: crate::Writable + crate::RegisterSpec,
237{
238    #[doc = "`0`"]
239    #[inline(always)]
240    pub fn stop(self) -> &'a mut crate::W<REG> {
241        self.variant(TX_DMA_EN_A::STOP)
242    }
243    #[doc = "`1`"]
244    #[inline(always)]
245    pub fn start(self) -> &'a mut crate::W<REG> {
246        self.variant(TX_DMA_EN_A::START)
247    }
248}
249#[doc = "Field `tx_dma_start` reader - Transmit DMA FSM Start"]
250pub type TX_DMA_START_R = crate::BitReader<TX_DMA_START_A>;
251#[doc = "Transmit DMA FSM Start\n\nValue on reset: 0"]
252#[derive(Clone, Copy, Debug, PartialEq, Eq)]
253pub enum TX_DMA_START_A {
254    #[doc = "0: `0`"]
255    NO_VALID = 0,
256    #[doc = "1: `1`"]
257    START = 1,
258}
259impl From<TX_DMA_START_A> for bool {
260    #[inline(always)]
261    fn from(variant: TX_DMA_START_A) -> Self {
262        variant as u8 != 0
263    }
264}
265impl TX_DMA_START_R {
266    #[doc = "Get enumerated values variant"]
267    #[inline(always)]
268    pub const fn variant(&self) -> TX_DMA_START_A {
269        match self.bits {
270            false => TX_DMA_START_A::NO_VALID,
271            true => TX_DMA_START_A::START,
272        }
273    }
274    #[doc = "`0`"]
275    #[inline(always)]
276    pub fn is_no_valid(&self) -> bool {
277        *self == TX_DMA_START_A::NO_VALID
278    }
279    #[doc = "`1`"]
280    #[inline(always)]
281    pub fn is_start(&self) -> bool {
282        *self == TX_DMA_START_A::START
283    }
284}
285#[doc = "Field `tx_dma_start` writer - Transmit DMA FSM Start"]
286pub type TX_DMA_START_W<'a, REG> = crate::BitWriter<'a, REG, TX_DMA_START_A>;
287impl<'a, REG> TX_DMA_START_W<'a, REG>
288where
289    REG: crate::Writable + crate::RegisterSpec,
290{
291    #[doc = "`0`"]
292    #[inline(always)]
293    pub fn no_valid(self) -> &'a mut crate::W<REG> {
294        self.variant(TX_DMA_START_A::NO_VALID)
295    }
296    #[doc = "`1`"]
297    #[inline(always)]
298    pub fn start(self) -> &'a mut crate::W<REG> {
299        self.variant(TX_DMA_START_A::START)
300    }
301}
302impl R {
303    #[doc = "Bit 0 - Flush the data in the TX FIFO"]
304    #[inline(always)]
305    pub fn flush_tx_fifo(&self) -> FLUSH_TX_FIFO_R {
306        FLUSH_TX_FIFO_R::new((self.bits & 1) != 0)
307    }
308    #[doc = "Bit 1 - Transmission Mode"]
309    #[inline(always)]
310    pub fn tx_md(&self) -> TX_MD_R {
311        TX_MD_R::new(((self.bits >> 1) & 1) != 0)
312    }
313    #[doc = "Bits 8:10 - Threshold value of TX DMA FIFO"]
314    #[inline(always)]
315    pub fn tx_th(&self) -> TX_TH_R {
316        TX_TH_R::new(((self.bits >> 8) & 7) as u8)
317    }
318    #[doc = "Bit 30 - Transmit DMA Enable"]
319    #[inline(always)]
320    pub fn tx_dma_en(&self) -> TX_DMA_EN_R {
321        TX_DMA_EN_R::new(((self.bits >> 30) & 1) != 0)
322    }
323    #[doc = "Bit 31 - Transmit DMA FSM Start"]
324    #[inline(always)]
325    pub fn tx_dma_start(&self) -> TX_DMA_START_R {
326        TX_DMA_START_R::new(((self.bits >> 31) & 1) != 0)
327    }
328}
329impl W {
330    #[doc = "Bit 0 - Flush the data in the TX FIFO"]
331    #[inline(always)]
332    #[must_use]
333    pub fn flush_tx_fifo(&mut self) -> FLUSH_TX_FIFO_W<EMAC_TX_CTL1_SPEC> {
334        FLUSH_TX_FIFO_W::new(self, 0)
335    }
336    #[doc = "Bit 1 - Transmission Mode"]
337    #[inline(always)]
338    #[must_use]
339    pub fn tx_md(&mut self) -> TX_MD_W<EMAC_TX_CTL1_SPEC> {
340        TX_MD_W::new(self, 1)
341    }
342    #[doc = "Bits 8:10 - Threshold value of TX DMA FIFO"]
343    #[inline(always)]
344    #[must_use]
345    pub fn tx_th(&mut self) -> TX_TH_W<EMAC_TX_CTL1_SPEC> {
346        TX_TH_W::new(self, 8)
347    }
348    #[doc = "Bit 30 - Transmit DMA Enable"]
349    #[inline(always)]
350    #[must_use]
351    pub fn tx_dma_en(&mut self) -> TX_DMA_EN_W<EMAC_TX_CTL1_SPEC> {
352        TX_DMA_EN_W::new(self, 30)
353    }
354    #[doc = "Bit 31 - Transmit DMA FSM Start"]
355    #[inline(always)]
356    #[must_use]
357    pub fn tx_dma_start(&mut self) -> TX_DMA_START_W<EMAC_TX_CTL1_SPEC> {
358        TX_DMA_START_W::new(self, 31)
359    }
360    #[doc = r" Writes raw bits to the register."]
361    #[doc = r""]
362    #[doc = r" # Safety"]
363    #[doc = r""]
364    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
365    #[inline(always)]
366    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
367        self.bits = bits;
368        self
369    }
370}
371#[doc = "EMAC Transmit Control Register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emac_tx_ctl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emac_tx_ctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
372pub struct EMAC_TX_CTL1_SPEC;
373impl crate::RegisterSpec for EMAC_TX_CTL1_SPEC {
374    type Ux = u32;
375}
376#[doc = "`read()` method returns [`emac_tx_ctl1::R`](R) reader structure"]
377impl crate::Readable for EMAC_TX_CTL1_SPEC {}
378#[doc = "`write(|w| ..)` method takes [`emac_tx_ctl1::W`](W) writer structure"]
379impl crate::Writable for EMAC_TX_CTL1_SPEC {
380    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
381    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
382}
383#[doc = "`reset()` method sets emac_tx_ctl1 to value 0"]
384impl crate::Resettable for EMAC_TX_CTL1_SPEC {
385    const RESET_VALUE: Self::Ux = 0;
386}
d1_pac/emac/emac_tx_ctl1.rs

d1_pac/emac/
emac_tx_ctl1.rs
