d1_pac/emac/
emac_rx_frm_flt.rs

1#[doc = "Register `emac_rx_frm_flt` reader"]
2pub type R = crate::R<EMAC_RX_FRM_FLT_SPEC>;
3#[doc = "Register `emac_rx_frm_flt` writer"]
4pub type W = crate::W<EMAC_RX_FRM_FLT_SPEC>;
5#[doc = "Field `rx_all` reader - Receive All Frame"]
6pub type RX_ALL_R = crate::BitReader<RX_ALL_A>;
7#[doc = "Receive All Frame\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum RX_ALL_A {
10    #[doc = "0: `0`"]
11    RECEIVE_WHEN_PASSED = 0,
12    #[doc = "1: `1`"]
13    RECEIVE_ALL_UPDATE = 1,
14}
15impl From<RX_ALL_A> for bool {
16    #[inline(always)]
17    fn from(variant: RX_ALL_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl RX_ALL_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> RX_ALL_A {
25        match self.bits {
26            false => RX_ALL_A::RECEIVE_WHEN_PASSED,
27            true => RX_ALL_A::RECEIVE_ALL_UPDATE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_receive_when_passed(&self) -> bool {
33        *self == RX_ALL_A::RECEIVE_WHEN_PASSED
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_receive_all_update(&self) -> bool {
38        *self == RX_ALL_A::RECEIVE_ALL_UPDATE
39    }
40}
41#[doc = "Field `rx_all` writer - Receive All Frame"]
42pub type RX_ALL_W<'a, REG> = crate::BitWriter<'a, REG, RX_ALL_A>;
43impl<'a, REG> RX_ALL_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn receive_when_passed(self) -> &'a mut crate::W<REG> {
50        self.variant(RX_ALL_A::RECEIVE_WHEN_PASSED)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn receive_all_update(self) -> &'a mut crate::W<REG> {
55        self.variant(RX_ALL_A::RECEIVE_ALL_UPDATE)
56    }
57}
58#[doc = "Field `flt_md` reader - "]
59pub type FLT_MD_R = crate::BitReader<FLT_MD_A>;
60#[doc = "\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum FLT_MD_A {
63    #[doc = "0: `0`"]
64    PASSED_WHEN_MATCHED = 0,
65    #[doc = "1: `1`"]
66    RECEIVE_WHEN_PASSED = 1,
67}
68impl From<FLT_MD_A> for bool {
69    #[inline(always)]
70    fn from(variant: FLT_MD_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl FLT_MD_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> FLT_MD_A {
78        match self.bits {
79            false => FLT_MD_A::PASSED_WHEN_MATCHED,
80            true => FLT_MD_A::RECEIVE_WHEN_PASSED,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_passed_when_matched(&self) -> bool {
86        *self == FLT_MD_A::PASSED_WHEN_MATCHED
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_receive_when_passed(&self) -> bool {
91        *self == FLT_MD_A::RECEIVE_WHEN_PASSED
92    }
93}
94#[doc = "Field `flt_md` writer - "]
95pub type FLT_MD_W<'a, REG> = crate::BitWriter<'a, REG, FLT_MD_A>;
96impl<'a, REG> FLT_MD_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn passed_when_matched(self) -> &'a mut crate::W<REG> {
103        self.variant(FLT_MD_A::PASSED_WHEN_MATCHED)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn receive_when_passed(self) -> &'a mut crate::W<REG> {
108        self.variant(FLT_MD_A::RECEIVE_WHEN_PASSED)
109    }
110}
111#[doc = "Field `da_inv_filter` reader - "]
112pub type DA_INV_FILTER_R = crate::BitReader<DA_INV_FILTER_A>;
113#[doc = "\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum DA_INV_FILTER_A {
116    #[doc = "0: `0`"]
117    NORMAL = 0,
118    #[doc = "1: `1`"]
119    INVERSE_CMP_DA = 1,
120}
121impl From<DA_INV_FILTER_A> for bool {
122    #[inline(always)]
123    fn from(variant: DA_INV_FILTER_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl DA_INV_FILTER_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> DA_INV_FILTER_A {
131        match self.bits {
132            false => DA_INV_FILTER_A::NORMAL,
133            true => DA_INV_FILTER_A::INVERSE_CMP_DA,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_normal(&self) -> bool {
139        *self == DA_INV_FILTER_A::NORMAL
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_inverse_cmp_da(&self) -> bool {
144        *self == DA_INV_FILTER_A::INVERSE_CMP_DA
145    }
146}
147#[doc = "Field `da_inv_filter` writer - "]
148pub type DA_INV_FILTER_W<'a, REG> = crate::BitWriter<'a, REG, DA_INV_FILTER_A>;
149impl<'a, REG> DA_INV_FILTER_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn normal(self) -> &'a mut crate::W<REG> {
156        self.variant(DA_INV_FILTER_A::NORMAL)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn inverse_cmp_da(self) -> &'a mut crate::W<REG> {
161        self.variant(DA_INV_FILTER_A::INVERSE_CMP_DA)
162    }
163}
164#[doc = "Field `sa_inv_filter` reader - Receive SA Invert Filter Set"]
165pub type SA_INV_FILTER_R = crate::BitReader<SA_INV_FILTER_A>;
166#[doc = "Receive SA Invert Filter Set\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum SA_INV_FILTER_A {
169    #[doc = "0: `0`"]
170    MATCHED = 0,
171    #[doc = "1: `1`"]
172    UNMATCHED = 1,
173}
174impl From<SA_INV_FILTER_A> for bool {
175    #[inline(always)]
176    fn from(variant: SA_INV_FILTER_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl SA_INV_FILTER_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> SA_INV_FILTER_A {
184        match self.bits {
185            false => SA_INV_FILTER_A::MATCHED,
186            true => SA_INV_FILTER_A::UNMATCHED,
187        }
188    }
189    #[doc = "`0`"]
190    #[inline(always)]
191    pub fn is_matched(&self) -> bool {
192        *self == SA_INV_FILTER_A::MATCHED
193    }
194    #[doc = "`1`"]
195    #[inline(always)]
196    pub fn is_unmatched(&self) -> bool {
197        *self == SA_INV_FILTER_A::UNMATCHED
198    }
199}
200#[doc = "Field `sa_inv_filter` writer - Receive SA Invert Filter Set"]
201pub type SA_INV_FILTER_W<'a, REG> = crate::BitWriter<'a, REG, SA_INV_FILTER_A>;
202impl<'a, REG> SA_INV_FILTER_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "`0`"]
207    #[inline(always)]
208    pub fn matched(self) -> &'a mut crate::W<REG> {
209        self.variant(SA_INV_FILTER_A::MATCHED)
210    }
211    #[doc = "`1`"]
212    #[inline(always)]
213    pub fn unmatched(self) -> &'a mut crate::W<REG> {
214        self.variant(SA_INV_FILTER_A::UNMATCHED)
215    }
216}
217#[doc = "Field `sa_filter_en` reader - Receive SA Filter Enable"]
218pub type SA_FILTER_EN_R = crate::BitReader<SA_FILTER_EN_A>;
219#[doc = "Receive SA Filter Enable\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221pub enum SA_FILTER_EN_A {
222    #[doc = "0: `0`"]
223    RECEIVE_UPDATE = 0,
224    #[doc = "1: `1`"]
225    UPDATE_DROP_UNMATCHED = 1,
226}
227impl From<SA_FILTER_EN_A> for bool {
228    #[inline(always)]
229    fn from(variant: SA_FILTER_EN_A) -> Self {
230        variant as u8 != 0
231    }
232}
233impl SA_FILTER_EN_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> SA_FILTER_EN_A {
237        match self.bits {
238            false => SA_FILTER_EN_A::RECEIVE_UPDATE,
239            true => SA_FILTER_EN_A::UPDATE_DROP_UNMATCHED,
240        }
241    }
242    #[doc = "`0`"]
243    #[inline(always)]
244    pub fn is_receive_update(&self) -> bool {
245        *self == SA_FILTER_EN_A::RECEIVE_UPDATE
246    }
247    #[doc = "`1`"]
248    #[inline(always)]
249    pub fn is_update_drop_unmatched(&self) -> bool {
250        *self == SA_FILTER_EN_A::UPDATE_DROP_UNMATCHED
251    }
252}
253#[doc = "Field `sa_filter_en` writer - Receive SA Filter Enable"]
254pub type SA_FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG, SA_FILTER_EN_A>;
255impl<'a, REG> SA_FILTER_EN_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "`0`"]
260    #[inline(always)]
261    pub fn receive_update(self) -> &'a mut crate::W<REG> {
262        self.variant(SA_FILTER_EN_A::RECEIVE_UPDATE)
263    }
264    #[doc = "`1`"]
265    #[inline(always)]
266    pub fn update_drop_unmatched(self) -> &'a mut crate::W<REG> {
267        self.variant(SA_FILTER_EN_A::UPDATE_DROP_UNMATCHED)
268    }
269}
270#[doc = "Field `hash_unicast` reader - Filter Unicast Frames Set"]
271pub type HASH_UNICAST_R = crate::BitReader<HASH_UNICAST_A>;
272#[doc = "Filter Unicast Frames Set\n\nValue on reset: 0"]
273#[derive(Clone, Copy, Debug, PartialEq, Eq)]
274pub enum HASH_UNICAST_A {
275    #[doc = "0: `0`"]
276    DA_FIELD = 0,
277    #[doc = "1: `1`"]
278    HASH_TABLE = 1,
279}
280impl From<HASH_UNICAST_A> for bool {
281    #[inline(always)]
282    fn from(variant: HASH_UNICAST_A) -> Self {
283        variant as u8 != 0
284    }
285}
286impl HASH_UNICAST_R {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> HASH_UNICAST_A {
290        match self.bits {
291            false => HASH_UNICAST_A::DA_FIELD,
292            true => HASH_UNICAST_A::HASH_TABLE,
293        }
294    }
295    #[doc = "`0`"]
296    #[inline(always)]
297    pub fn is_da_field(&self) -> bool {
298        *self == HASH_UNICAST_A::DA_FIELD
299    }
300    #[doc = "`1`"]
301    #[inline(always)]
302    pub fn is_hash_table(&self) -> bool {
303        *self == HASH_UNICAST_A::HASH_TABLE
304    }
305}
306#[doc = "Field `hash_unicast` writer - Filter Unicast Frames Set"]
307pub type HASH_UNICAST_W<'a, REG> = crate::BitWriter<'a, REG, HASH_UNICAST_A>;
308impl<'a, REG> HASH_UNICAST_W<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "`0`"]
313    #[inline(always)]
314    pub fn da_field(self) -> &'a mut crate::W<REG> {
315        self.variant(HASH_UNICAST_A::DA_FIELD)
316    }
317    #[doc = "`1`"]
318    #[inline(always)]
319    pub fn hash_table(self) -> &'a mut crate::W<REG> {
320        self.variant(HASH_UNICAST_A::HASH_TABLE)
321    }
322}
323#[doc = "Field `hash_multicast` reader - Filter Multicast Frames Set"]
324pub type HASH_MULTICAST_R = crate::BitReader<HASH_MULTICAST_A>;
325#[doc = "Filter Multicast Frames Set\n\nValue on reset: 0"]
326#[derive(Clone, Copy, Debug, PartialEq, Eq)]
327pub enum HASH_MULTICAST_A {
328    #[doc = "0: `0`"]
329    DA_FIELD = 0,
330    #[doc = "1: `1`"]
331    HASH_TABLE = 1,
332}
333impl From<HASH_MULTICAST_A> for bool {
334    #[inline(always)]
335    fn from(variant: HASH_MULTICAST_A) -> Self {
336        variant as u8 != 0
337    }
338}
339impl HASH_MULTICAST_R {
340    #[doc = "Get enumerated values variant"]
341    #[inline(always)]
342    pub const fn variant(&self) -> HASH_MULTICAST_A {
343        match self.bits {
344            false => HASH_MULTICAST_A::DA_FIELD,
345            true => HASH_MULTICAST_A::HASH_TABLE,
346        }
347    }
348    #[doc = "`0`"]
349    #[inline(always)]
350    pub fn is_da_field(&self) -> bool {
351        *self == HASH_MULTICAST_A::DA_FIELD
352    }
353    #[doc = "`1`"]
354    #[inline(always)]
355    pub fn is_hash_table(&self) -> bool {
356        *self == HASH_MULTICAST_A::HASH_TABLE
357    }
358}
359#[doc = "Field `hash_multicast` writer - Filter Multicast Frames Set"]
360pub type HASH_MULTICAST_W<'a, REG> = crate::BitWriter<'a, REG, HASH_MULTICAST_A>;
361impl<'a, REG> HASH_MULTICAST_W<'a, REG>
362where
363    REG: crate::Writable + crate::RegisterSpec,
364{
365    #[doc = "`0`"]
366    #[inline(always)]
367    pub fn da_field(self) -> &'a mut crate::W<REG> {
368        self.variant(HASH_MULTICAST_A::DA_FIELD)
369    }
370    #[doc = "`1`"]
371    #[inline(always)]
372    pub fn hash_table(self) -> &'a mut crate::W<REG> {
373        self.variant(HASH_MULTICAST_A::HASH_TABLE)
374    }
375}
376#[doc = "Field `ctl_frm_filter` reader - Receive Control Frames Filter"]
377pub type CTL_FRM_FILTER_R = crate::FieldReader<CTL_FRM_FILTER_A>;
378#[doc = "Receive Control Frames Filter\n\nValue on reset: 0"]
379#[derive(Clone, Copy, Debug, PartialEq, Eq)]
380#[repr(u8)]
381pub enum CTL_FRM_FILTER_A {
382    #[doc = "0: `0`"]
383    DROP_ALL = 0,
384    #[doc = "2: `10`"]
385    RECEIVE_ALL = 2,
386    #[doc = "3: `11`"]
387    RECEIVE_ALL_WHEN_FILTER = 3,
388}
389impl From<CTL_FRM_FILTER_A> for u8 {
390    #[inline(always)]
391    fn from(variant: CTL_FRM_FILTER_A) -> Self {
392        variant as _
393    }
394}
395impl crate::FieldSpec for CTL_FRM_FILTER_A {
396    type Ux = u8;
397}
398impl CTL_FRM_FILTER_R {
399    #[doc = "Get enumerated values variant"]
400    #[inline(always)]
401    pub const fn variant(&self) -> Option<CTL_FRM_FILTER_A> {
402        match self.bits {
403            0 => Some(CTL_FRM_FILTER_A::DROP_ALL),
404            2 => Some(CTL_FRM_FILTER_A::RECEIVE_ALL),
405            3 => Some(CTL_FRM_FILTER_A::RECEIVE_ALL_WHEN_FILTER),
406            _ => None,
407        }
408    }
409    #[doc = "`0`"]
410    #[inline(always)]
411    pub fn is_drop_all(&self) -> bool {
412        *self == CTL_FRM_FILTER_A::DROP_ALL
413    }
414    #[doc = "`10`"]
415    #[inline(always)]
416    pub fn is_receive_all(&self) -> bool {
417        *self == CTL_FRM_FILTER_A::RECEIVE_ALL
418    }
419    #[doc = "`11`"]
420    #[inline(always)]
421    pub fn is_receive_all_when_filter(&self) -> bool {
422        *self == CTL_FRM_FILTER_A::RECEIVE_ALL_WHEN_FILTER
423    }
424}
425#[doc = "Field `ctl_frm_filter` writer - Receive Control Frames Filter"]
426pub type CTL_FRM_FILTER_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CTL_FRM_FILTER_A>;
427impl<'a, REG> CTL_FRM_FILTER_W<'a, REG>
428where
429    REG: crate::Writable + crate::RegisterSpec,
430    REG::Ux: From<u8>,
431{
432    #[doc = "`0`"]
433    #[inline(always)]
434    pub fn drop_all(self) -> &'a mut crate::W<REG> {
435        self.variant(CTL_FRM_FILTER_A::DROP_ALL)
436    }
437    #[doc = "`10`"]
438    #[inline(always)]
439    pub fn receive_all(self) -> &'a mut crate::W<REG> {
440        self.variant(CTL_FRM_FILTER_A::RECEIVE_ALL)
441    }
442    #[doc = "`11`"]
443    #[inline(always)]
444    pub fn receive_all_when_filter(self) -> &'a mut crate::W<REG> {
445        self.variant(CTL_FRM_FILTER_A::RECEIVE_ALL_WHEN_FILTER)
446    }
447}
448#[doc = "Field `rx_all_multicast` reader - Receive All Multicast Frames Filter"]
449pub type RX_ALL_MULTICAST_R = crate::BitReader<RX_ALL_MULTICAST_A>;
450#[doc = "Receive All Multicast Frames Filter\n\nValue on reset: 0"]
451#[derive(Clone, Copy, Debug, PartialEq, Eq)]
452pub enum RX_ALL_MULTICAST_A {
453    #[doc = "0: `0`"]
454    FILTER = 0,
455    #[doc = "1: `1`"]
456    RECEIVE_ALL = 1,
457}
458impl From<RX_ALL_MULTICAST_A> for bool {
459    #[inline(always)]
460    fn from(variant: RX_ALL_MULTICAST_A) -> Self {
461        variant as u8 != 0
462    }
463}
464impl RX_ALL_MULTICAST_R {
465    #[doc = "Get enumerated values variant"]
466    #[inline(always)]
467    pub const fn variant(&self) -> RX_ALL_MULTICAST_A {
468        match self.bits {
469            false => RX_ALL_MULTICAST_A::FILTER,
470            true => RX_ALL_MULTICAST_A::RECEIVE_ALL,
471        }
472    }
473    #[doc = "`0`"]
474    #[inline(always)]
475    pub fn is_filter(&self) -> bool {
476        *self == RX_ALL_MULTICAST_A::FILTER
477    }
478    #[doc = "`1`"]
479    #[inline(always)]
480    pub fn is_receive_all(&self) -> bool {
481        *self == RX_ALL_MULTICAST_A::RECEIVE_ALL
482    }
483}
484#[doc = "Field `rx_all_multicast` writer - Receive All Multicast Frames Filter"]
485pub type RX_ALL_MULTICAST_W<'a, REG> = crate::BitWriter<'a, REG, RX_ALL_MULTICAST_A>;
486impl<'a, REG> RX_ALL_MULTICAST_W<'a, REG>
487where
488    REG: crate::Writable + crate::RegisterSpec,
489{
490    #[doc = "`0`"]
491    #[inline(always)]
492    pub fn filter(self) -> &'a mut crate::W<REG> {
493        self.variant(RX_ALL_MULTICAST_A::FILTER)
494    }
495    #[doc = "`1`"]
496    #[inline(always)]
497    pub fn receive_all(self) -> &'a mut crate::W<REG> {
498        self.variant(RX_ALL_MULTICAST_A::RECEIVE_ALL)
499    }
500}
501#[doc = "Field `dis_broadcast` reader - Disable Receive Broadcast Frames"]
502pub type DIS_BROADCAST_R = crate::BitReader<DIS_BROADCAST_A>;
503#[doc = "Disable Receive Broadcast Frames\n\nValue on reset: 0"]
504#[derive(Clone, Copy, Debug, PartialEq, Eq)]
505pub enum DIS_BROADCAST_A {
506    #[doc = "0: `0`"]
507    RECEIVE = 0,
508    #[doc = "1: `1`"]
509    DROP = 1,
510}
511impl From<DIS_BROADCAST_A> for bool {
512    #[inline(always)]
513    fn from(variant: DIS_BROADCAST_A) -> Self {
514        variant as u8 != 0
515    }
516}
517impl DIS_BROADCAST_R {
518    #[doc = "Get enumerated values variant"]
519    #[inline(always)]
520    pub const fn variant(&self) -> DIS_BROADCAST_A {
521        match self.bits {
522            false => DIS_BROADCAST_A::RECEIVE,
523            true => DIS_BROADCAST_A::DROP,
524        }
525    }
526    #[doc = "`0`"]
527    #[inline(always)]
528    pub fn is_receive(&self) -> bool {
529        *self == DIS_BROADCAST_A::RECEIVE
530    }
531    #[doc = "`1`"]
532    #[inline(always)]
533    pub fn is_drop(&self) -> bool {
534        *self == DIS_BROADCAST_A::DROP
535    }
536}
537#[doc = "Field `dis_broadcast` writer - Disable Receive Broadcast Frames"]
538pub type DIS_BROADCAST_W<'a, REG> = crate::BitWriter<'a, REG, DIS_BROADCAST_A>;
539impl<'a, REG> DIS_BROADCAST_W<'a, REG>
540where
541    REG: crate::Writable + crate::RegisterSpec,
542{
543    #[doc = "`0`"]
544    #[inline(always)]
545    pub fn receive(self) -> &'a mut crate::W<REG> {
546        self.variant(DIS_BROADCAST_A::RECEIVE)
547    }
548    #[doc = "`1`"]
549    #[inline(always)]
550    pub fn drop(self) -> &'a mut crate::W<REG> {
551        self.variant(DIS_BROADCAST_A::DROP)
552    }
553}
554#[doc = "Field `dis_addr_filter` reader - Disable Address Filter"]
555pub type DIS_ADDR_FILTER_R = crate::BitReader<DIS_ADDR_FILTER_A>;
556#[doc = "Disable Address Filter\n\nValue on reset: 0"]
557#[derive(Clone, Copy, Debug, PartialEq, Eq)]
558pub enum DIS_ADDR_FILTER_A {
559    #[doc = "0: `0`"]
560    ENABLE = 0,
561    #[doc = "1: `1`"]
562    DISABLE = 1,
563}
564impl From<DIS_ADDR_FILTER_A> for bool {
565    #[inline(always)]
566    fn from(variant: DIS_ADDR_FILTER_A) -> Self {
567        variant as u8 != 0
568    }
569}
570impl DIS_ADDR_FILTER_R {
571    #[doc = "Get enumerated values variant"]
572    #[inline(always)]
573    pub const fn variant(&self) -> DIS_ADDR_FILTER_A {
574        match self.bits {
575            false => DIS_ADDR_FILTER_A::ENABLE,
576            true => DIS_ADDR_FILTER_A::DISABLE,
577        }
578    }
579    #[doc = "`0`"]
580    #[inline(always)]
581    pub fn is_enable(&self) -> bool {
582        *self == DIS_ADDR_FILTER_A::ENABLE
583    }
584    #[doc = "`1`"]
585    #[inline(always)]
586    pub fn is_disable(&self) -> bool {
587        *self == DIS_ADDR_FILTER_A::DISABLE
588    }
589}
590#[doc = "Field `dis_addr_filter` writer - Disable Address Filter"]
591pub type DIS_ADDR_FILTER_W<'a, REG> = crate::BitWriter<'a, REG, DIS_ADDR_FILTER_A>;
592impl<'a, REG> DIS_ADDR_FILTER_W<'a, REG>
593where
594    REG: crate::Writable + crate::RegisterSpec,
595{
596    #[doc = "`0`"]
597    #[inline(always)]
598    pub fn enable(self) -> &'a mut crate::W<REG> {
599        self.variant(DIS_ADDR_FILTER_A::ENABLE)
600    }
601    #[doc = "`1`"]
602    #[inline(always)]
603    pub fn disable(self) -> &'a mut crate::W<REG> {
604        self.variant(DIS_ADDR_FILTER_A::DISABLE)
605    }
606}
607impl R {
608    #[doc = "Bit 0 - Receive All Frame"]
609    #[inline(always)]
610    pub fn rx_all(&self) -> RX_ALL_R {
611        RX_ALL_R::new((self.bits & 1) != 0)
612    }
613    #[doc = "Bit 1"]
614    #[inline(always)]
615    pub fn flt_md(&self) -> FLT_MD_R {
616        FLT_MD_R::new(((self.bits >> 1) & 1) != 0)
617    }
618    #[doc = "Bit 4"]
619    #[inline(always)]
620    pub fn da_inv_filter(&self) -> DA_INV_FILTER_R {
621        DA_INV_FILTER_R::new(((self.bits >> 4) & 1) != 0)
622    }
623    #[doc = "Bit 5 - Receive SA Invert Filter Set"]
624    #[inline(always)]
625    pub fn sa_inv_filter(&self) -> SA_INV_FILTER_R {
626        SA_INV_FILTER_R::new(((self.bits >> 5) & 1) != 0)
627    }
628    #[doc = "Bit 6 - Receive SA Filter Enable"]
629    #[inline(always)]
630    pub fn sa_filter_en(&self) -> SA_FILTER_EN_R {
631        SA_FILTER_EN_R::new(((self.bits >> 6) & 1) != 0)
632    }
633    #[doc = "Bit 8 - Filter Unicast Frames Set"]
634    #[inline(always)]
635    pub fn hash_unicast(&self) -> HASH_UNICAST_R {
636        HASH_UNICAST_R::new(((self.bits >> 8) & 1) != 0)
637    }
638    #[doc = "Bit 9 - Filter Multicast Frames Set"]
639    #[inline(always)]
640    pub fn hash_multicast(&self) -> HASH_MULTICAST_R {
641        HASH_MULTICAST_R::new(((self.bits >> 9) & 1) != 0)
642    }
643    #[doc = "Bits 12:13 - Receive Control Frames Filter"]
644    #[inline(always)]
645    pub fn ctl_frm_filter(&self) -> CTL_FRM_FILTER_R {
646        CTL_FRM_FILTER_R::new(((self.bits >> 12) & 3) as u8)
647    }
648    #[doc = "Bit 16 - Receive All Multicast Frames Filter"]
649    #[inline(always)]
650    pub fn rx_all_multicast(&self) -> RX_ALL_MULTICAST_R {
651        RX_ALL_MULTICAST_R::new(((self.bits >> 16) & 1) != 0)
652    }
653    #[doc = "Bit 17 - Disable Receive Broadcast Frames"]
654    #[inline(always)]
655    pub fn dis_broadcast(&self) -> DIS_BROADCAST_R {
656        DIS_BROADCAST_R::new(((self.bits >> 17) & 1) != 0)
657    }
658    #[doc = "Bit 31 - Disable Address Filter"]
659    #[inline(always)]
660    pub fn dis_addr_filter(&self) -> DIS_ADDR_FILTER_R {
661        DIS_ADDR_FILTER_R::new(((self.bits >> 31) & 1) != 0)
662    }
663}
664impl W {
665    #[doc = "Bit 0 - Receive All Frame"]
666    #[inline(always)]
667    #[must_use]
668    pub fn rx_all(&mut self) -> RX_ALL_W<EMAC_RX_FRM_FLT_SPEC> {
669        RX_ALL_W::new(self, 0)
670    }
671    #[doc = "Bit 1"]
672    #[inline(always)]
673    #[must_use]
674    pub fn flt_md(&mut self) -> FLT_MD_W<EMAC_RX_FRM_FLT_SPEC> {
675        FLT_MD_W::new(self, 1)
676    }
677    #[doc = "Bit 4"]
678    #[inline(always)]
679    #[must_use]
680    pub fn da_inv_filter(&mut self) -> DA_INV_FILTER_W<EMAC_RX_FRM_FLT_SPEC> {
681        DA_INV_FILTER_W::new(self, 4)
682    }
683    #[doc = "Bit 5 - Receive SA Invert Filter Set"]
684    #[inline(always)]
685    #[must_use]
686    pub fn sa_inv_filter(&mut self) -> SA_INV_FILTER_W<EMAC_RX_FRM_FLT_SPEC> {
687        SA_INV_FILTER_W::new(self, 5)
688    }
689    #[doc = "Bit 6 - Receive SA Filter Enable"]
690    #[inline(always)]
691    #[must_use]
692    pub fn sa_filter_en(&mut self) -> SA_FILTER_EN_W<EMAC_RX_FRM_FLT_SPEC> {
693        SA_FILTER_EN_W::new(self, 6)
694    }
695    #[doc = "Bit 8 - Filter Unicast Frames Set"]
696    #[inline(always)]
697    #[must_use]
698    pub fn hash_unicast(&mut self) -> HASH_UNICAST_W<EMAC_RX_FRM_FLT_SPEC> {
699        HASH_UNICAST_W::new(self, 8)
700    }
701    #[doc = "Bit 9 - Filter Multicast Frames Set"]
702    #[inline(always)]
703    #[must_use]
704    pub fn hash_multicast(&mut self) -> HASH_MULTICAST_W<EMAC_RX_FRM_FLT_SPEC> {
705        HASH_MULTICAST_W::new(self, 9)
706    }
707    #[doc = "Bits 12:13 - Receive Control Frames Filter"]
708    #[inline(always)]
709    #[must_use]
710    pub fn ctl_frm_filter(&mut self) -> CTL_FRM_FILTER_W<EMAC_RX_FRM_FLT_SPEC> {
711        CTL_FRM_FILTER_W::new(self, 12)
712    }
713    #[doc = "Bit 16 - Receive All Multicast Frames Filter"]
714    #[inline(always)]
715    #[must_use]
716    pub fn rx_all_multicast(&mut self) -> RX_ALL_MULTICAST_W<EMAC_RX_FRM_FLT_SPEC> {
717        RX_ALL_MULTICAST_W::new(self, 16)
718    }
719    #[doc = "Bit 17 - Disable Receive Broadcast Frames"]
720    #[inline(always)]
721    #[must_use]
722    pub fn dis_broadcast(&mut self) -> DIS_BROADCAST_W<EMAC_RX_FRM_FLT_SPEC> {
723        DIS_BROADCAST_W::new(self, 17)
724    }
725    #[doc = "Bit 31 - Disable Address Filter"]
726    #[inline(always)]
727    #[must_use]
728    pub fn dis_addr_filter(&mut self) -> DIS_ADDR_FILTER_W<EMAC_RX_FRM_FLT_SPEC> {
729        DIS_ADDR_FILTER_W::new(self, 31)
730    }
731    #[doc = r" Writes raw bits to the register."]
732    #[doc = r""]
733    #[doc = r" # Safety"]
734    #[doc = r""]
735    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
736    #[inline(always)]
737    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
738        self.bits = bits;
739        self
740    }
741}
742#[doc = "EMAC Receive Frame Filter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emac_rx_frm_flt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emac_rx_frm_flt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
743pub struct EMAC_RX_FRM_FLT_SPEC;
744impl crate::RegisterSpec for EMAC_RX_FRM_FLT_SPEC {
745    type Ux = u32;
746}
747#[doc = "`read()` method returns [`emac_rx_frm_flt::R`](R) reader structure"]
748impl crate::Readable for EMAC_RX_FRM_FLT_SPEC {}
749#[doc = "`write(|w| ..)` method takes [`emac_rx_frm_flt::W`](W) writer structure"]
750impl crate::Writable for EMAC_RX_FRM_FLT_SPEC {
751    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
752    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
753}
754#[doc = "`reset()` method sets emac_rx_frm_flt to value 0"]
755impl crate::Resettable for EMAC_RX_FRM_FLT_SPEC {
756    const RESET_VALUE: Self::Ux = 0;
757}
d1_pac/emac/emac_rx_frm_flt.rs

d1_pac/emac/
emac_rx_frm_flt.rs
