1#[doc = "Register `emac_rx_ctl1` reader"]
2pub type R = crate::R<EMAC_RX_CTL1_SPEC>;
3#[doc = "Register `emac_rx_ctl1` writer"]
4pub type W = crate::W<EMAC_RX_CTL1_SPEC>;
5#[doc = "Field `flush_rx_frm` reader - Flush Receive Frames"]
6pub type FLUSH_RX_FRM_R = crate::BitReader<FLUSH_RX_FRM_A>;
7#[doc = "Flush Receive Frames\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum FLUSH_RX_FRM_A {
10 #[doc = "0: `0`"]
11 ENABLE = 0,
12 #[doc = "1: `1`"]
13 DISABLE = 1,
14}
15impl From<FLUSH_RX_FRM_A> for bool {
16 #[inline(always)]
17 fn from(variant: FLUSH_RX_FRM_A) -> Self {
18 variant as u8 != 0
19 }
20}
21impl FLUSH_RX_FRM_R {
22 #[doc = "Get enumerated values variant"]
23 #[inline(always)]
24 pub const fn variant(&self) -> FLUSH_RX_FRM_A {
25 match self.bits {
26 false => FLUSH_RX_FRM_A::ENABLE,
27 true => FLUSH_RX_FRM_A::DISABLE,
28 }
29 }
30 #[doc = "`0`"]
31 #[inline(always)]
32 pub fn is_enable(&self) -> bool {
33 *self == FLUSH_RX_FRM_A::ENABLE
34 }
35 #[doc = "`1`"]
36 #[inline(always)]
37 pub fn is_disable(&self) -> bool {
38 *self == FLUSH_RX_FRM_A::DISABLE
39 }
40}
41#[doc = "Field `flush_rx_frm` writer - Flush Receive Frames"]
42pub type FLUSH_RX_FRM_W<'a, REG> = crate::BitWriter<'a, REG, FLUSH_RX_FRM_A>;
43impl<'a, REG> FLUSH_RX_FRM_W<'a, REG>
44where
45 REG: crate::Writable + crate::RegisterSpec,
46{
47 #[doc = "`0`"]
48 #[inline(always)]
49 pub fn enable(self) -> &'a mut crate::W<REG> {
50 self.variant(FLUSH_RX_FRM_A::ENABLE)
51 }
52 #[doc = "`1`"]
53 #[inline(always)]
54 pub fn disable(self) -> &'a mut crate::W<REG> {
55 self.variant(FLUSH_RX_FRM_A::DISABLE)
56 }
57}
58#[doc = "Field `rx_md` reader - Receive Mode"]
59pub type RX_MD_R = crate::BitReader<RX_MD_A>;
60#[doc = "Receive Mode\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum RX_MD_A {
63 #[doc = "0: `0`"]
64 GREATER_THAN_TH = 0,
65 #[doc = "1: `1`"]
66 LOCATE_FULL_FRAME = 1,
67}
68impl From<RX_MD_A> for bool {
69 #[inline(always)]
70 fn from(variant: RX_MD_A) -> Self {
71 variant as u8 != 0
72 }
73}
74impl RX_MD_R {
75 #[doc = "Get enumerated values variant"]
76 #[inline(always)]
77 pub const fn variant(&self) -> RX_MD_A {
78 match self.bits {
79 false => RX_MD_A::GREATER_THAN_TH,
80 true => RX_MD_A::LOCATE_FULL_FRAME,
81 }
82 }
83 #[doc = "`0`"]
84 #[inline(always)]
85 pub fn is_greater_than_th(&self) -> bool {
86 *self == RX_MD_A::GREATER_THAN_TH
87 }
88 #[doc = "`1`"]
89 #[inline(always)]
90 pub fn is_locate_full_frame(&self) -> bool {
91 *self == RX_MD_A::LOCATE_FULL_FRAME
92 }
93}
94#[doc = "Field `rx_md` writer - Receive Mode"]
95pub type RX_MD_W<'a, REG> = crate::BitWriter<'a, REG, RX_MD_A>;
96impl<'a, REG> RX_MD_W<'a, REG>
97where
98 REG: crate::Writable + crate::RegisterSpec,
99{
100 #[doc = "`0`"]
101 #[inline(always)]
102 pub fn greater_than_th(self) -> &'a mut crate::W<REG> {
103 self.variant(RX_MD_A::GREATER_THAN_TH)
104 }
105 #[doc = "`1`"]
106 #[inline(always)]
107 pub fn locate_full_frame(self) -> &'a mut crate::W<REG> {
108 self.variant(RX_MD_A::LOCATE_FULL_FRAME)
109 }
110}
111#[doc = "Field `rx_runt_frm` reader - "]
112pub type RX_RUNT_FRM_R = crate::BitReader;
113#[doc = "Field `rx_runt_frm` writer - "]
114pub type RX_RUNT_FRM_W<'a, REG> = crate::BitWriter<'a, REG>;
115#[doc = "Field `rx_err_frm` reader - "]
116pub type RX_ERR_FRM_R = crate::BitReader<RX_ERR_FRM_A>;
117#[doc = "\n\nValue on reset: 0"]
118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
119pub enum RX_ERR_FRM_A {
120 #[doc = "0: `0`"]
121 DROP = 0,
122 #[doc = "1: `1`"]
123 FORWARD = 1,
124}
125impl From<RX_ERR_FRM_A> for bool {
126 #[inline(always)]
127 fn from(variant: RX_ERR_FRM_A) -> Self {
128 variant as u8 != 0
129 }
130}
131impl RX_ERR_FRM_R {
132 #[doc = "Get enumerated values variant"]
133 #[inline(always)]
134 pub const fn variant(&self) -> RX_ERR_FRM_A {
135 match self.bits {
136 false => RX_ERR_FRM_A::DROP,
137 true => RX_ERR_FRM_A::FORWARD,
138 }
139 }
140 #[doc = "`0`"]
141 #[inline(always)]
142 pub fn is_drop(&self) -> bool {
143 *self == RX_ERR_FRM_A::DROP
144 }
145 #[doc = "`1`"]
146 #[inline(always)]
147 pub fn is_forward(&self) -> bool {
148 *self == RX_ERR_FRM_A::FORWARD
149 }
150}
151#[doc = "Field `rx_err_frm` writer - "]
152pub type RX_ERR_FRM_W<'a, REG> = crate::BitWriter<'a, REG, RX_ERR_FRM_A>;
153impl<'a, REG> RX_ERR_FRM_W<'a, REG>
154where
155 REG: crate::Writable + crate::RegisterSpec,
156{
157 #[doc = "`0`"]
158 #[inline(always)]
159 pub fn drop(self) -> &'a mut crate::W<REG> {
160 self.variant(RX_ERR_FRM_A::DROP)
161 }
162 #[doc = "`1`"]
163 #[inline(always)]
164 pub fn forward(self) -> &'a mut crate::W<REG> {
165 self.variant(RX_ERR_FRM_A::FORWARD)
166 }
167}
168#[doc = "Field `rx_th` reader - Threshold for RX DMA FIFO Start"]
169pub type RX_TH_R = crate::FieldReader<RX_TH_A>;
170#[doc = "Threshold for RX DMA FIFO Start\n\nValue on reset: 0"]
171#[derive(Clone, Copy, Debug, PartialEq, Eq)]
172#[repr(u8)]
173pub enum RX_TH_A {
174 #[doc = "0: `0`"]
175 T64 = 0,
176 #[doc = "1: `1`"]
177 T32 = 1,
178 #[doc = "2: `10`"]
179 T96 = 2,
180 #[doc = "3: `11`"]
181 T128 = 3,
182}
183impl From<RX_TH_A> for u8 {
184 #[inline(always)]
185 fn from(variant: RX_TH_A) -> Self {
186 variant as _
187 }
188}
189impl crate::FieldSpec for RX_TH_A {
190 type Ux = u8;
191}
192impl RX_TH_R {
193 #[doc = "Get enumerated values variant"]
194 #[inline(always)]
195 pub const fn variant(&self) -> RX_TH_A {
196 match self.bits {
197 0 => RX_TH_A::T64,
198 1 => RX_TH_A::T32,
199 2 => RX_TH_A::T96,
200 3 => RX_TH_A::T128,
201 _ => unreachable!(),
202 }
203 }
204 #[doc = "`0`"]
205 #[inline(always)]
206 pub fn is_t64(&self) -> bool {
207 *self == RX_TH_A::T64
208 }
209 #[doc = "`1`"]
210 #[inline(always)]
211 pub fn is_t32(&self) -> bool {
212 *self == RX_TH_A::T32
213 }
214 #[doc = "`10`"]
215 #[inline(always)]
216 pub fn is_t96(&self) -> bool {
217 *self == RX_TH_A::T96
218 }
219 #[doc = "`11`"]
220 #[inline(always)]
221 pub fn is_t128(&self) -> bool {
222 *self == RX_TH_A::T128
223 }
224}
225#[doc = "Field `rx_th` writer - Threshold for RX DMA FIFO Start"]
226pub type RX_TH_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, RX_TH_A>;
227impl<'a, REG> RX_TH_W<'a, REG>
228where
229 REG: crate::Writable + crate::RegisterSpec,
230 REG::Ux: From<u8>,
231{
232 #[doc = "`0`"]
233 #[inline(always)]
234 pub fn t64(self) -> &'a mut crate::W<REG> {
235 self.variant(RX_TH_A::T64)
236 }
237 #[doc = "`1`"]
238 #[inline(always)]
239 pub fn t32(self) -> &'a mut crate::W<REG> {
240 self.variant(RX_TH_A::T32)
241 }
242 #[doc = "`10`"]
243 #[inline(always)]
244 pub fn t96(self) -> &'a mut crate::W<REG> {
245 self.variant(RX_TH_A::T96)
246 }
247 #[doc = "`11`"]
248 #[inline(always)]
249 pub fn t128(self) -> &'a mut crate::W<REG> {
250 self.variant(RX_TH_A::T128)
251 }
252}
253#[doc = "Field `rx_flow_ctl_th_act` reader - Threshold for Activating Flow Control"]
254pub type RX_FLOW_CTL_TH_ACT_R = crate::FieldReader<RX_FLOW_CTL_TH_ACT_A>;
255#[doc = "Threshold for Activating Flow Control\n\nValue on reset: 0"]
256#[derive(Clone, Copy, Debug, PartialEq, Eq)]
257#[repr(u8)]
258pub enum RX_FLOW_CTL_TH_ACT_A {
259 #[doc = "0: `0`"]
260 FM1K = 0,
261 #[doc = "1: `1`"]
262 FM2K = 1,
263 #[doc = "2: `10`"]
264 FM3K = 2,
265 #[doc = "3: `11`"]
266 FM4K = 3,
267}
268impl From<RX_FLOW_CTL_TH_ACT_A> for u8 {
269 #[inline(always)]
270 fn from(variant: RX_FLOW_CTL_TH_ACT_A) -> Self {
271 variant as _
272 }
273}
274impl crate::FieldSpec for RX_FLOW_CTL_TH_ACT_A {
275 type Ux = u8;
276}
277impl RX_FLOW_CTL_TH_ACT_R {
278 #[doc = "Get enumerated values variant"]
279 #[inline(always)]
280 pub const fn variant(&self) -> RX_FLOW_CTL_TH_ACT_A {
281 match self.bits {
282 0 => RX_FLOW_CTL_TH_ACT_A::FM1K,
283 1 => RX_FLOW_CTL_TH_ACT_A::FM2K,
284 2 => RX_FLOW_CTL_TH_ACT_A::FM3K,
285 3 => RX_FLOW_CTL_TH_ACT_A::FM4K,
286 _ => unreachable!(),
287 }
288 }
289 #[doc = "`0`"]
290 #[inline(always)]
291 pub fn is_fm1k(&self) -> bool {
292 *self == RX_FLOW_CTL_TH_ACT_A::FM1K
293 }
294 #[doc = "`1`"]
295 #[inline(always)]
296 pub fn is_fm2k(&self) -> bool {
297 *self == RX_FLOW_CTL_TH_ACT_A::FM2K
298 }
299 #[doc = "`10`"]
300 #[inline(always)]
301 pub fn is_fm3k(&self) -> bool {
302 *self == RX_FLOW_CTL_TH_ACT_A::FM3K
303 }
304 #[doc = "`11`"]
305 #[inline(always)]
306 pub fn is_fm4k(&self) -> bool {
307 *self == RX_FLOW_CTL_TH_ACT_A::FM4K
308 }
309}
310#[doc = "Field `rx_flow_ctl_th_act` writer - Threshold for Activating Flow Control"]
311pub type RX_FLOW_CTL_TH_ACT_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, RX_FLOW_CTL_TH_ACT_A>;
312impl<'a, REG> RX_FLOW_CTL_TH_ACT_W<'a, REG>
313where
314 REG: crate::Writable + crate::RegisterSpec,
315 REG::Ux: From<u8>,
316{
317 #[doc = "`0`"]
318 #[inline(always)]
319 pub fn fm1k(self) -> &'a mut crate::W<REG> {
320 self.variant(RX_FLOW_CTL_TH_ACT_A::FM1K)
321 }
322 #[doc = "`1`"]
323 #[inline(always)]
324 pub fn fm2k(self) -> &'a mut crate::W<REG> {
325 self.variant(RX_FLOW_CTL_TH_ACT_A::FM2K)
326 }
327 #[doc = "`10`"]
328 #[inline(always)]
329 pub fn fm3k(self) -> &'a mut crate::W<REG> {
330 self.variant(RX_FLOW_CTL_TH_ACT_A::FM3K)
331 }
332 #[doc = "`11`"]
333 #[inline(always)]
334 pub fn fm4k(self) -> &'a mut crate::W<REG> {
335 self.variant(RX_FLOW_CTL_TH_ACT_A::FM4K)
336 }
337}
338#[doc = "Field `rx_flow_ctl_th_deact` reader - Threshold for Deactivating Flow Control"]
339pub type RX_FLOW_CTL_TH_DEACT_R = crate::FieldReader<RX_FLOW_CTL_TH_DEACT_A>;
340#[doc = "Threshold for Deactivating Flow Control\n\nValue on reset: 0"]
341#[derive(Clone, Copy, Debug, PartialEq, Eq)]
342#[repr(u8)]
343pub enum RX_FLOW_CTL_TH_DEACT_A {
344 #[doc = "0: `0`"]
345 FM1K = 0,
346 #[doc = "1: `1`"]
347 FM2K = 1,
348 #[doc = "2: `10`"]
349 FM3K = 2,
350 #[doc = "3: `11`"]
351 FM4K = 3,
352}
353impl From<RX_FLOW_CTL_TH_DEACT_A> for u8 {
354 #[inline(always)]
355 fn from(variant: RX_FLOW_CTL_TH_DEACT_A) -> Self {
356 variant as _
357 }
358}
359impl crate::FieldSpec for RX_FLOW_CTL_TH_DEACT_A {
360 type Ux = u8;
361}
362impl RX_FLOW_CTL_TH_DEACT_R {
363 #[doc = "Get enumerated values variant"]
364 #[inline(always)]
365 pub const fn variant(&self) -> RX_FLOW_CTL_TH_DEACT_A {
366 match self.bits {
367 0 => RX_FLOW_CTL_TH_DEACT_A::FM1K,
368 1 => RX_FLOW_CTL_TH_DEACT_A::FM2K,
369 2 => RX_FLOW_CTL_TH_DEACT_A::FM3K,
370 3 => RX_FLOW_CTL_TH_DEACT_A::FM4K,
371 _ => unreachable!(),
372 }
373 }
374 #[doc = "`0`"]
375 #[inline(always)]
376 pub fn is_fm1k(&self) -> bool {
377 *self == RX_FLOW_CTL_TH_DEACT_A::FM1K
378 }
379 #[doc = "`1`"]
380 #[inline(always)]
381 pub fn is_fm2k(&self) -> bool {
382 *self == RX_FLOW_CTL_TH_DEACT_A::FM2K
383 }
384 #[doc = "`10`"]
385 #[inline(always)]
386 pub fn is_fm3k(&self) -> bool {
387 *self == RX_FLOW_CTL_TH_DEACT_A::FM3K
388 }
389 #[doc = "`11`"]
390 #[inline(always)]
391 pub fn is_fm4k(&self) -> bool {
392 *self == RX_FLOW_CTL_TH_DEACT_A::FM4K
393 }
394}
395#[doc = "Field `rx_flow_ctl_th_deact` writer - Threshold for Deactivating Flow Control"]
396pub type RX_FLOW_CTL_TH_DEACT_W<'a, REG> =
397 crate::FieldWriterSafe<'a, REG, 2, RX_FLOW_CTL_TH_DEACT_A>;
398impl<'a, REG> RX_FLOW_CTL_TH_DEACT_W<'a, REG>
399where
400 REG: crate::Writable + crate::RegisterSpec,
401 REG::Ux: From<u8>,
402{
403 #[doc = "`0`"]
404 #[inline(always)]
405 pub fn fm1k(self) -> &'a mut crate::W<REG> {
406 self.variant(RX_FLOW_CTL_TH_DEACT_A::FM1K)
407 }
408 #[doc = "`1`"]
409 #[inline(always)]
410 pub fn fm2k(self) -> &'a mut crate::W<REG> {
411 self.variant(RX_FLOW_CTL_TH_DEACT_A::FM2K)
412 }
413 #[doc = "`10`"]
414 #[inline(always)]
415 pub fn fm3k(self) -> &'a mut crate::W<REG> {
416 self.variant(RX_FLOW_CTL_TH_DEACT_A::FM3K)
417 }
418 #[doc = "`11`"]
419 #[inline(always)]
420 pub fn fm4k(self) -> &'a mut crate::W<REG> {
421 self.variant(RX_FLOW_CTL_TH_DEACT_A::FM4K)
422 }
423}
424#[doc = "Field `rx_fifo_flow_ctl` reader - Receive FIFO Flow Control Enable"]
425pub type RX_FIFO_FLOW_CTL_R = crate::BitReader<RX_FIFO_FLOW_CTL_A>;
426#[doc = "Receive FIFO Flow Control Enable\n\nValue on reset: 0"]
427#[derive(Clone, Copy, Debug, PartialEq, Eq)]
428pub enum RX_FIFO_FLOW_CTL_A {
429 #[doc = "0: `0`"]
430 DISABLE = 0,
431 #[doc = "1: `1`"]
432 ENABLE = 1,
433}
434impl From<RX_FIFO_FLOW_CTL_A> for bool {
435 #[inline(always)]
436 fn from(variant: RX_FIFO_FLOW_CTL_A) -> Self {
437 variant as u8 != 0
438 }
439}
440impl RX_FIFO_FLOW_CTL_R {
441 #[doc = "Get enumerated values variant"]
442 #[inline(always)]
443 pub const fn variant(&self) -> RX_FIFO_FLOW_CTL_A {
444 match self.bits {
445 false => RX_FIFO_FLOW_CTL_A::DISABLE,
446 true => RX_FIFO_FLOW_CTL_A::ENABLE,
447 }
448 }
449 #[doc = "`0`"]
450 #[inline(always)]
451 pub fn is_disable(&self) -> bool {
452 *self == RX_FIFO_FLOW_CTL_A::DISABLE
453 }
454 #[doc = "`1`"]
455 #[inline(always)]
456 pub fn is_enable(&self) -> bool {
457 *self == RX_FIFO_FLOW_CTL_A::ENABLE
458 }
459}
460#[doc = "Field `rx_fifo_flow_ctl` writer - Receive FIFO Flow Control Enable"]
461pub type RX_FIFO_FLOW_CTL_W<'a, REG> = crate::BitWriter<'a, REG, RX_FIFO_FLOW_CTL_A>;
462impl<'a, REG> RX_FIFO_FLOW_CTL_W<'a, REG>
463where
464 REG: crate::Writable + crate::RegisterSpec,
465{
466 #[doc = "`0`"]
467 #[inline(always)]
468 pub fn disable(self) -> &'a mut crate::W<REG> {
469 self.variant(RX_FIFO_FLOW_CTL_A::DISABLE)
470 }
471 #[doc = "`1`"]
472 #[inline(always)]
473 pub fn enable(self) -> &'a mut crate::W<REG> {
474 self.variant(RX_FIFO_FLOW_CTL_A::ENABLE)
475 }
476}
477#[doc = "Field `rx_ema_en` reader - Receive DMA Enable"]
478pub type RX_EMA_EN_R = crate::BitReader<RX_EMA_EN_A>;
479#[doc = "Receive DMA Enable\n\nValue on reset: 0"]
480#[derive(Clone, Copy, Debug, PartialEq, Eq)]
481pub enum RX_EMA_EN_A {
482 #[doc = "0: `0`"]
483 STOP = 0,
484 #[doc = "1: `1`"]
485 START = 1,
486}
487impl From<RX_EMA_EN_A> for bool {
488 #[inline(always)]
489 fn from(variant: RX_EMA_EN_A) -> Self {
490 variant as u8 != 0
491 }
492}
493impl RX_EMA_EN_R {
494 #[doc = "Get enumerated values variant"]
495 #[inline(always)]
496 pub const fn variant(&self) -> RX_EMA_EN_A {
497 match self.bits {
498 false => RX_EMA_EN_A::STOP,
499 true => RX_EMA_EN_A::START,
500 }
501 }
502 #[doc = "`0`"]
503 #[inline(always)]
504 pub fn is_stop(&self) -> bool {
505 *self == RX_EMA_EN_A::STOP
506 }
507 #[doc = "`1`"]
508 #[inline(always)]
509 pub fn is_start(&self) -> bool {
510 *self == RX_EMA_EN_A::START
511 }
512}
513#[doc = "Field `rx_ema_en` writer - Receive DMA Enable"]
514pub type RX_EMA_EN_W<'a, REG> = crate::BitWriter<'a, REG, RX_EMA_EN_A>;
515impl<'a, REG> RX_EMA_EN_W<'a, REG>
516where
517 REG: crate::Writable + crate::RegisterSpec,
518{
519 #[doc = "`0`"]
520 #[inline(always)]
521 pub fn stop(self) -> &'a mut crate::W<REG> {
522 self.variant(RX_EMA_EN_A::STOP)
523 }
524 #[doc = "`1`"]
525 #[inline(always)]
526 pub fn start(self) -> &'a mut crate::W<REG> {
527 self.variant(RX_EMA_EN_A::START)
528 }
529}
530#[doc = "Field `rx_dma_start` reader - "]
531pub type RX_DMA_START_R = crate::BitReader;
532#[doc = "Field `rx_dma_start` writer - "]
533pub type RX_DMA_START_W<'a, REG> = crate::BitWriter<'a, REG>;
534impl R {
535 #[doc = "Bit 0 - Flush Receive Frames"]
536 #[inline(always)]
537 pub fn flush_rx_frm(&self) -> FLUSH_RX_FRM_R {
538 FLUSH_RX_FRM_R::new((self.bits & 1) != 0)
539 }
540 #[doc = "Bit 1 - Receive Mode"]
541 #[inline(always)]
542 pub fn rx_md(&self) -> RX_MD_R {
543 RX_MD_R::new(((self.bits >> 1) & 1) != 0)
544 }
545 #[doc = "Bit 2"]
546 #[inline(always)]
547 pub fn rx_runt_frm(&self) -> RX_RUNT_FRM_R {
548 RX_RUNT_FRM_R::new(((self.bits >> 2) & 1) != 0)
549 }
550 #[doc = "Bit 3"]
551 #[inline(always)]
552 pub fn rx_err_frm(&self) -> RX_ERR_FRM_R {
553 RX_ERR_FRM_R::new(((self.bits >> 3) & 1) != 0)
554 }
555 #[doc = "Bits 4:5 - Threshold for RX DMA FIFO Start"]
556 #[inline(always)]
557 pub fn rx_th(&self) -> RX_TH_R {
558 RX_TH_R::new(((self.bits >> 4) & 3) as u8)
559 }
560 #[doc = "Bits 20:21 - Threshold for Activating Flow Control"]
561 #[inline(always)]
562 pub fn rx_flow_ctl_th_act(&self) -> RX_FLOW_CTL_TH_ACT_R {
563 RX_FLOW_CTL_TH_ACT_R::new(((self.bits >> 20) & 3) as u8)
564 }
565 #[doc = "Bits 22:23 - Threshold for Deactivating Flow Control"]
566 #[inline(always)]
567 pub fn rx_flow_ctl_th_deact(&self) -> RX_FLOW_CTL_TH_DEACT_R {
568 RX_FLOW_CTL_TH_DEACT_R::new(((self.bits >> 22) & 3) as u8)
569 }
570 #[doc = "Bit 24 - Receive FIFO Flow Control Enable"]
571 #[inline(always)]
572 pub fn rx_fifo_flow_ctl(&self) -> RX_FIFO_FLOW_CTL_R {
573 RX_FIFO_FLOW_CTL_R::new(((self.bits >> 24) & 1) != 0)
574 }
575 #[doc = "Bit 30 - Receive DMA Enable"]
576 #[inline(always)]
577 pub fn rx_ema_en(&self) -> RX_EMA_EN_R {
578 RX_EMA_EN_R::new(((self.bits >> 30) & 1) != 0)
579 }
580 #[doc = "Bit 31"]
581 #[inline(always)]
582 pub fn rx_dma_start(&self) -> RX_DMA_START_R {
583 RX_DMA_START_R::new(((self.bits >> 31) & 1) != 0)
584 }
585}
586impl W {
587 #[doc = "Bit 0 - Flush Receive Frames"]
588 #[inline(always)]
589 #[must_use]
590 pub fn flush_rx_frm(&mut self) -> FLUSH_RX_FRM_W<EMAC_RX_CTL1_SPEC> {
591 FLUSH_RX_FRM_W::new(self, 0)
592 }
593 #[doc = "Bit 1 - Receive Mode"]
594 #[inline(always)]
595 #[must_use]
596 pub fn rx_md(&mut self) -> RX_MD_W<EMAC_RX_CTL1_SPEC> {
597 RX_MD_W::new(self, 1)
598 }
599 #[doc = "Bit 2"]
600 #[inline(always)]
601 #[must_use]
602 pub fn rx_runt_frm(&mut self) -> RX_RUNT_FRM_W<EMAC_RX_CTL1_SPEC> {
603 RX_RUNT_FRM_W::new(self, 2)
604 }
605 #[doc = "Bit 3"]
606 #[inline(always)]
607 #[must_use]
608 pub fn rx_err_frm(&mut self) -> RX_ERR_FRM_W<EMAC_RX_CTL1_SPEC> {
609 RX_ERR_FRM_W::new(self, 3)
610 }
611 #[doc = "Bits 4:5 - Threshold for RX DMA FIFO Start"]
612 #[inline(always)]
613 #[must_use]
614 pub fn rx_th(&mut self) -> RX_TH_W<EMAC_RX_CTL1_SPEC> {
615 RX_TH_W::new(self, 4)
616 }
617 #[doc = "Bits 20:21 - Threshold for Activating Flow Control"]
618 #[inline(always)]
619 #[must_use]
620 pub fn rx_flow_ctl_th_act(&mut self) -> RX_FLOW_CTL_TH_ACT_W<EMAC_RX_CTL1_SPEC> {
621 RX_FLOW_CTL_TH_ACT_W::new(self, 20)
622 }
623 #[doc = "Bits 22:23 - Threshold for Deactivating Flow Control"]
624 #[inline(always)]
625 #[must_use]
626 pub fn rx_flow_ctl_th_deact(&mut self) -> RX_FLOW_CTL_TH_DEACT_W<EMAC_RX_CTL1_SPEC> {
627 RX_FLOW_CTL_TH_DEACT_W::new(self, 22)
628 }
629 #[doc = "Bit 24 - Receive FIFO Flow Control Enable"]
630 #[inline(always)]
631 #[must_use]
632 pub fn rx_fifo_flow_ctl(&mut self) -> RX_FIFO_FLOW_CTL_W<EMAC_RX_CTL1_SPEC> {
633 RX_FIFO_FLOW_CTL_W::new(self, 24)
634 }
635 #[doc = "Bit 30 - Receive DMA Enable"]
636 #[inline(always)]
637 #[must_use]
638 pub fn rx_ema_en(&mut self) -> RX_EMA_EN_W<EMAC_RX_CTL1_SPEC> {
639 RX_EMA_EN_W::new(self, 30)
640 }
641 #[doc = "Bit 31"]
642 #[inline(always)]
643 #[must_use]
644 pub fn rx_dma_start(&mut self) -> RX_DMA_START_W<EMAC_RX_CTL1_SPEC> {
645 RX_DMA_START_W::new(self, 31)
646 }
647 #[doc = r" Writes raw bits to the register."]
648 #[doc = r""]
649 #[doc = r" # Safety"]
650 #[doc = r""]
651 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
652 #[inline(always)]
653 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
654 self.bits = bits;
655 self
656 }
657}
658#[doc = "EMAC Receive Control Register1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emac_rx_ctl1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emac_rx_ctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
659pub struct EMAC_RX_CTL1_SPEC;
660impl crate::RegisterSpec for EMAC_RX_CTL1_SPEC {
661 type Ux = u32;
662}
663#[doc = "`read()` method returns [`emac_rx_ctl1::R`](R) reader structure"]
664impl crate::Readable for EMAC_RX_CTL1_SPEC {}
665#[doc = "`write(|w| ..)` method takes [`emac_rx_ctl1::W`](W) writer structure"]
666impl crate::Writable for EMAC_RX_CTL1_SPEC {
667 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
668 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
669}
670#[doc = "`reset()` method sets emac_rx_ctl1 to value 0"]
671impl crate::Resettable for EMAC_RX_CTL1_SPEC {
672 const RESET_VALUE: Self::Ux = 0;
673}