d1_pac/emac/
emac_mii_cmd.rs

1#[doc = "Register `emac_mii_cmd` reader"]
2pub type R = crate::R<EMAC_MII_CMD_SPEC>;
3#[doc = "Register `emac_mii_cmd` writer"]
4pub type W = crate::W<EMAC_MII_CMD_SPEC>;
5#[doc = "Field `mii_busy` reader - MII Status"]
6pub type MII_BUSY_R = crate::BitReader;
7#[doc = "Field `mii_busy` writer - MII Status"]
8pub type MII_BUSY_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `mii_wr` reader - MII Write and Read"]
10pub type MII_WR_R = crate::BitReader<MII_WR_A>;
11#[doc = "MII Write and Read\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum MII_WR_A {
14    #[doc = "0: `0`"]
15    R = 0,
16    #[doc = "1: `1`"]
17    W = 1,
18}
19impl From<MII_WR_A> for bool {
20    #[inline(always)]
21    fn from(variant: MII_WR_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl MII_WR_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> MII_WR_A {
29        match self.bits {
30            false => MII_WR_A::R,
31            true => MII_WR_A::W,
32        }
33    }
34    #[doc = "`0`"]
35    #[inline(always)]
36    pub fn is_r(&self) -> bool {
37        *self == MII_WR_A::R
38    }
39    #[doc = "`1`"]
40    #[inline(always)]
41    pub fn is_w(&self) -> bool {
42        *self == MII_WR_A::W
43    }
44}
45#[doc = "Field `mii_wr` writer - MII Write and Read"]
46pub type MII_WR_W<'a, REG> = crate::BitWriter<'a, REG, MII_WR_A>;
47impl<'a, REG> MII_WR_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "`0`"]
52    #[inline(always)]
53    pub fn r(self) -> &'a mut crate::W<REG> {
54        self.variant(MII_WR_A::R)
55    }
56    #[doc = "`1`"]
57    #[inline(always)]
58    pub fn w(self) -> &'a mut crate::W<REG> {
59        self.variant(MII_WR_A::W)
60    }
61}
62#[doc = "Field `phy_reg_addr` reader - PHY Register Address"]
63pub type PHY_REG_ADDR_R = crate::FieldReader;
64#[doc = "Field `phy_reg_addr` writer - PHY Register Address"]
65pub type PHY_REG_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
66#[doc = "Field `phy_addr` reader - PHY Address"]
67pub type PHY_ADDR_R = crate::FieldReader;
68#[doc = "Field `phy_addr` writer - PHY Address"]
69pub type PHY_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
70#[doc = "Field `mdc_div_ratio_m` reader - MDC Clock DIvider Ratio"]
71pub type MDC_DIV_RATIO_M_R = crate::FieldReader<MDC_DIV_RATIO_M_A>;
72#[doc = "MDC Clock DIvider Ratio\n\nValue on reset: 0"]
73#[derive(Clone, Copy, Debug, PartialEq, Eq)]
74#[repr(u8)]
75pub enum MDC_DIV_RATIO_M_A {
76    #[doc = "0: `0`"]
77    R16 = 0,
78    #[doc = "1: `1`"]
79    R32 = 1,
80    #[doc = "2: `10`"]
81    R64 = 2,
82    #[doc = "3: `11`"]
83    R128 = 3,
84}
85impl From<MDC_DIV_RATIO_M_A> for u8 {
86    #[inline(always)]
87    fn from(variant: MDC_DIV_RATIO_M_A) -> Self {
88        variant as _
89    }
90}
91impl crate::FieldSpec for MDC_DIV_RATIO_M_A {
92    type Ux = u8;
93}
94impl MDC_DIV_RATIO_M_R {
95    #[doc = "Get enumerated values variant"]
96    #[inline(always)]
97    pub const fn variant(&self) -> Option<MDC_DIV_RATIO_M_A> {
98        match self.bits {
99            0 => Some(MDC_DIV_RATIO_M_A::R16),
100            1 => Some(MDC_DIV_RATIO_M_A::R32),
101            2 => Some(MDC_DIV_RATIO_M_A::R64),
102            3 => Some(MDC_DIV_RATIO_M_A::R128),
103            _ => None,
104        }
105    }
106    #[doc = "`0`"]
107    #[inline(always)]
108    pub fn is_r16(&self) -> bool {
109        *self == MDC_DIV_RATIO_M_A::R16
110    }
111    #[doc = "`1`"]
112    #[inline(always)]
113    pub fn is_r32(&self) -> bool {
114        *self == MDC_DIV_RATIO_M_A::R32
115    }
116    #[doc = "`10`"]
117    #[inline(always)]
118    pub fn is_r64(&self) -> bool {
119        *self == MDC_DIV_RATIO_M_A::R64
120    }
121    #[doc = "`11`"]
122    #[inline(always)]
123    pub fn is_r128(&self) -> bool {
124        *self == MDC_DIV_RATIO_M_A::R128
125    }
126}
127#[doc = "Field `mdc_div_ratio_m` writer - MDC Clock DIvider Ratio"]
128pub type MDC_DIV_RATIO_M_W<'a, REG> = crate::FieldWriter<'a, REG, 3, MDC_DIV_RATIO_M_A>;
129impl<'a, REG> MDC_DIV_RATIO_M_W<'a, REG>
130where
131    REG: crate::Writable + crate::RegisterSpec,
132    REG::Ux: From<u8>,
133{
134    #[doc = "`0`"]
135    #[inline(always)]
136    pub fn r16(self) -> &'a mut crate::W<REG> {
137        self.variant(MDC_DIV_RATIO_M_A::R16)
138    }
139    #[doc = "`1`"]
140    #[inline(always)]
141    pub fn r32(self) -> &'a mut crate::W<REG> {
142        self.variant(MDC_DIV_RATIO_M_A::R32)
143    }
144    #[doc = "`10`"]
145    #[inline(always)]
146    pub fn r64(self) -> &'a mut crate::W<REG> {
147        self.variant(MDC_DIV_RATIO_M_A::R64)
148    }
149    #[doc = "`11`"]
150    #[inline(always)]
151    pub fn r128(self) -> &'a mut crate::W<REG> {
152        self.variant(MDC_DIV_RATIO_M_A::R128)
153    }
154}
155impl R {
156    #[doc = "Bit 0 - MII Status"]
157    #[inline(always)]
158    pub fn mii_busy(&self) -> MII_BUSY_R {
159        MII_BUSY_R::new((self.bits & 1) != 0)
160    }
161    #[doc = "Bit 1 - MII Write and Read"]
162    #[inline(always)]
163    pub fn mii_wr(&self) -> MII_WR_R {
164        MII_WR_R::new(((self.bits >> 1) & 1) != 0)
165    }
166    #[doc = "Bits 4:8 - PHY Register Address"]
167    #[inline(always)]
168    pub fn phy_reg_addr(&self) -> PHY_REG_ADDR_R {
169        PHY_REG_ADDR_R::new(((self.bits >> 4) & 0x1f) as u8)
170    }
171    #[doc = "Bits 12:16 - PHY Address"]
172    #[inline(always)]
173    pub fn phy_addr(&self) -> PHY_ADDR_R {
174        PHY_ADDR_R::new(((self.bits >> 12) & 0x1f) as u8)
175    }
176    #[doc = "Bits 20:22 - MDC Clock DIvider Ratio"]
177    #[inline(always)]
178    pub fn mdc_div_ratio_m(&self) -> MDC_DIV_RATIO_M_R {
179        MDC_DIV_RATIO_M_R::new(((self.bits >> 20) & 7) as u8)
180    }
181}
182impl W {
183    #[doc = "Bit 0 - MII Status"]
184    #[inline(always)]
185    #[must_use]
186    pub fn mii_busy(&mut self) -> MII_BUSY_W<EMAC_MII_CMD_SPEC> {
187        MII_BUSY_W::new(self, 0)
188    }
189    #[doc = "Bit 1 - MII Write and Read"]
190    #[inline(always)]
191    #[must_use]
192    pub fn mii_wr(&mut self) -> MII_WR_W<EMAC_MII_CMD_SPEC> {
193        MII_WR_W::new(self, 1)
194    }
195    #[doc = "Bits 4:8 - PHY Register Address"]
196    #[inline(always)]
197    #[must_use]
198    pub fn phy_reg_addr(&mut self) -> PHY_REG_ADDR_W<EMAC_MII_CMD_SPEC> {
199        PHY_REG_ADDR_W::new(self, 4)
200    }
201    #[doc = "Bits 12:16 - PHY Address"]
202    #[inline(always)]
203    #[must_use]
204    pub fn phy_addr(&mut self) -> PHY_ADDR_W<EMAC_MII_CMD_SPEC> {
205        PHY_ADDR_W::new(self, 12)
206    }
207    #[doc = "Bits 20:22 - MDC Clock DIvider Ratio"]
208    #[inline(always)]
209    #[must_use]
210    pub fn mdc_div_ratio_m(&mut self) -> MDC_DIV_RATIO_M_W<EMAC_MII_CMD_SPEC> {
211        MDC_DIV_RATIO_M_W::new(self, 20)
212    }
213    #[doc = r" Writes raw bits to the register."]
214    #[doc = r""]
215    #[doc = r" # Safety"]
216    #[doc = r""]
217    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
218    #[inline(always)]
219    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
220        self.bits = bits;
221        self
222    }
223}
224#[doc = "EMAC Management Interface Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emac_mii_cmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emac_mii_cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
225pub struct EMAC_MII_CMD_SPEC;
226impl crate::RegisterSpec for EMAC_MII_CMD_SPEC {
227    type Ux = u32;
228}
229#[doc = "`read()` method returns [`emac_mii_cmd::R`](R) reader structure"]
230impl crate::Readable for EMAC_MII_CMD_SPEC {}
231#[doc = "`write(|w| ..)` method takes [`emac_mii_cmd::W`](W) writer structure"]
232impl crate::Writable for EMAC_MII_CMD_SPEC {
233    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
234    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
235}
236#[doc = "`reset()` method sets emac_mii_cmd to value 0"]
237impl crate::Resettable for EMAC_MII_CMD_SPEC {
238    const RESET_VALUE: Self::Ux = 0;
239}
d1_pac/emac/emac_mii_cmd.rs

d1_pac/emac/
emac_mii_cmd.rs
