d1_pac/emac/
emac_addr_high.rs

1#[doc = "Register `emac_addr_high%s` reader"]
2pub type R = crate::R<EMAC_ADDR_HIGH_SPEC>;
3#[doc = "Register `emac_addr_high%s` writer"]
4pub type W = crate::W<EMAC_ADDR_HIGH_SPEC>;
5#[doc = "Field `mac_addr_high` reader - "]
6pub type MAC_ADDR_HIGH_R = crate::FieldReader<u16>;
7#[doc = "Field `mac_addr_high` writer - "]
8pub type MAC_ADDR_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `mac_addr_byte_ctl` reader - MAC Address Byte Control Mask"]
10pub type MAC_ADDR_BYTE_CTL_R = crate::FieldReader;
11#[doc = "Field `mac_addr_byte_ctl` writer - MAC Address Byte Control Mask"]
12pub type MAC_ADDR_BYTE_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `mac_addr_type` reader - MAC Address Type"]
14pub type MAC_ADDR_TYPE_R = crate::BitReader<MAC_ADDR_TYPE_A>;
15#[doc = "MAC Address Type\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17pub enum MAC_ADDR_TYPE_A {
18    #[doc = "0: `0`"]
19    DST = 0,
20    #[doc = "1: `1`"]
21    SRC = 1,
22}
23impl From<MAC_ADDR_TYPE_A> for bool {
24    #[inline(always)]
25    fn from(variant: MAC_ADDR_TYPE_A) -> Self {
26        variant as u8 != 0
27    }
28}
29impl MAC_ADDR_TYPE_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> MAC_ADDR_TYPE_A {
33        match self.bits {
34            false => MAC_ADDR_TYPE_A::DST,
35            true => MAC_ADDR_TYPE_A::SRC,
36        }
37    }
38    #[doc = "`0`"]
39    #[inline(always)]
40    pub fn is_dst(&self) -> bool {
41        *self == MAC_ADDR_TYPE_A::DST
42    }
43    #[doc = "`1`"]
44    #[inline(always)]
45    pub fn is_src(&self) -> bool {
46        *self == MAC_ADDR_TYPE_A::SRC
47    }
48}
49#[doc = "Field `mac_addr_type` writer - MAC Address Type"]
50pub type MAC_ADDR_TYPE_W<'a, REG> = crate::BitWriter<'a, REG, MAC_ADDR_TYPE_A>;
51impl<'a, REG> MAC_ADDR_TYPE_W<'a, REG>
52where
53    REG: crate::Writable + crate::RegisterSpec,
54{
55    #[doc = "`0`"]
56    #[inline(always)]
57    pub fn dst(self) -> &'a mut crate::W<REG> {
58        self.variant(MAC_ADDR_TYPE_A::DST)
59    }
60    #[doc = "`1`"]
61    #[inline(always)]
62    pub fn src(self) -> &'a mut crate::W<REG> {
63        self.variant(MAC_ADDR_TYPE_A::SRC)
64    }
65}
66#[doc = "Field `mac_addr_ctl` reader - MAC Address Valid"]
67pub type MAC_ADDR_CTL_R = crate::BitReader<MAC_ADDR_CTL_A>;
68#[doc = "MAC Address Valid\n\nValue on reset: 0"]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum MAC_ADDR_CTL_A {
71    #[doc = "0: `0`"]
72    INVALID = 0,
73    #[doc = "1: `1`"]
74    VALID = 1,
75}
76impl From<MAC_ADDR_CTL_A> for bool {
77    #[inline(always)]
78    fn from(variant: MAC_ADDR_CTL_A) -> Self {
79        variant as u8 != 0
80    }
81}
82impl MAC_ADDR_CTL_R {
83    #[doc = "Get enumerated values variant"]
84    #[inline(always)]
85    pub const fn variant(&self) -> MAC_ADDR_CTL_A {
86        match self.bits {
87            false => MAC_ADDR_CTL_A::INVALID,
88            true => MAC_ADDR_CTL_A::VALID,
89        }
90    }
91    #[doc = "`0`"]
92    #[inline(always)]
93    pub fn is_invalid(&self) -> bool {
94        *self == MAC_ADDR_CTL_A::INVALID
95    }
96    #[doc = "`1`"]
97    #[inline(always)]
98    pub fn is_valid(&self) -> bool {
99        *self == MAC_ADDR_CTL_A::VALID
100    }
101}
102#[doc = "Field `mac_addr_ctl` writer - MAC Address Valid"]
103pub type MAC_ADDR_CTL_W<'a, REG> = crate::BitWriter<'a, REG, MAC_ADDR_CTL_A>;
104impl<'a, REG> MAC_ADDR_CTL_W<'a, REG>
105where
106    REG: crate::Writable + crate::RegisterSpec,
107{
108    #[doc = "`0`"]
109    #[inline(always)]
110    pub fn invalid(self) -> &'a mut crate::W<REG> {
111        self.variant(MAC_ADDR_CTL_A::INVALID)
112    }
113    #[doc = "`1`"]
114    #[inline(always)]
115    pub fn valid(self) -> &'a mut crate::W<REG> {
116        self.variant(MAC_ADDR_CTL_A::VALID)
117    }
118}
119impl R {
120    #[doc = "Bits 0:15"]
121    #[inline(always)]
122    pub fn mac_addr_high(&self) -> MAC_ADDR_HIGH_R {
123        MAC_ADDR_HIGH_R::new((self.bits & 0xffff) as u16)
124    }
125    #[doc = "Bits 24:29 - MAC Address Byte Control Mask"]
126    #[inline(always)]
127    pub fn mac_addr_byte_ctl(&self) -> MAC_ADDR_BYTE_CTL_R {
128        MAC_ADDR_BYTE_CTL_R::new(((self.bits >> 24) & 0x3f) as u8)
129    }
130    #[doc = "Bit 30 - MAC Address Type"]
131    #[inline(always)]
132    pub fn mac_addr_type(&self) -> MAC_ADDR_TYPE_R {
133        MAC_ADDR_TYPE_R::new(((self.bits >> 30) & 1) != 0)
134    }
135    #[doc = "Bit 31 - MAC Address Valid"]
136    #[inline(always)]
137    pub fn mac_addr_ctl(&self) -> MAC_ADDR_CTL_R {
138        MAC_ADDR_CTL_R::new(((self.bits >> 31) & 1) != 0)
139    }
140}
141impl W {
142    #[doc = "Bits 0:15"]
143    #[inline(always)]
144    #[must_use]
145    pub fn mac_addr_high(&mut self) -> MAC_ADDR_HIGH_W<EMAC_ADDR_HIGH_SPEC> {
146        MAC_ADDR_HIGH_W::new(self, 0)
147    }
148    #[doc = "Bits 24:29 - MAC Address Byte Control Mask"]
149    #[inline(always)]
150    #[must_use]
151    pub fn mac_addr_byte_ctl(&mut self) -> MAC_ADDR_BYTE_CTL_W<EMAC_ADDR_HIGH_SPEC> {
152        MAC_ADDR_BYTE_CTL_W::new(self, 24)
153    }
154    #[doc = "Bit 30 - MAC Address Type"]
155    #[inline(always)]
156    #[must_use]
157    pub fn mac_addr_type(&mut self) -> MAC_ADDR_TYPE_W<EMAC_ADDR_HIGH_SPEC> {
158        MAC_ADDR_TYPE_W::new(self, 30)
159    }
160    #[doc = "Bit 31 - MAC Address Valid"]
161    #[inline(always)]
162    #[must_use]
163    pub fn mac_addr_ctl(&mut self) -> MAC_ADDR_CTL_W<EMAC_ADDR_HIGH_SPEC> {
164        MAC_ADDR_CTL_W::new(self, 31)
165    }
166    #[doc = r" Writes raw bits to the register."]
167    #[doc = r""]
168    #[doc = r" # Safety"]
169    #[doc = r""]
170    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
171    #[inline(always)]
172    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
173        self.bits = bits;
174        self
175    }
176}
177#[doc = "EMAC MAC Address High Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emac_addr_high::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emac_addr_high::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
178pub struct EMAC_ADDR_HIGH_SPEC;
179impl crate::RegisterSpec for EMAC_ADDR_HIGH_SPEC {
180    type Ux = u32;
181}
182#[doc = "`read()` method returns [`emac_addr_high::R`](R) reader structure"]
183impl crate::Readable for EMAC_ADDR_HIGH_SPEC {}
184#[doc = "`write(|w| ..)` method takes [`emac_addr_high::W`](W) writer structure"]
185impl crate::Writable for EMAC_ADDR_HIGH_SPEC {
186    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
187    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
188}
189#[doc = "`reset()` method sets emac_addr_high%s to value 0"]
190impl crate::Resettable for EMAC_ADDR_HIGH_SPEC {
191    const RESET_VALUE: Self::Ux = 0;
192}
d1_pac/emac/emac_addr_high.rs

d1_pac/emac/
emac_addr_high.rs
