d1_pac/dsp_msgbox/msgbox/
msgbox_wr_irq_status.rs

1#[doc = "Register `msgbox_wr_irq_status` reader"]
2pub type R = crate::R<MSGBOX_WR_IRQ_STATUS_SPEC>;
3#[doc = "Register `msgbox_wr_irq_status` writer"]
4pub type W = crate::W<MSGBOX_WR_IRQ_STATUS_SPEC>;
5#[doc = "Field `transmit_mq_irq_pend[0-3]` reader - Transmit Channel\\[i\\] Interrupt Pending"]
6pub type TRANSMIT_MQ_IRQ_PEND_R = crate::BitReader<TRANSMIT_MQ_IRQ_PEND_A>;
7#[doc = "Transmit Channel\\[i\\] Interrupt Pending\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TRANSMIT_MQ_IRQ_PEND_A {
10    #[doc = "0: No effect"]
11    NO_EFFECT = 0,
12    #[doc = "1: Pending"]
13    PENDING = 1,
14}
15impl From<TRANSMIT_MQ_IRQ_PEND_A> for bool {
16    #[inline(always)]
17    fn from(variant: TRANSMIT_MQ_IRQ_PEND_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl TRANSMIT_MQ_IRQ_PEND_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> TRANSMIT_MQ_IRQ_PEND_A {
25        match self.bits {
26            false => TRANSMIT_MQ_IRQ_PEND_A::NO_EFFECT,
27            true => TRANSMIT_MQ_IRQ_PEND_A::PENDING,
28        }
29    }
30    #[doc = "No effect"]
31    #[inline(always)]
32    pub fn is_no_effect(&self) -> bool {
33        *self == TRANSMIT_MQ_IRQ_PEND_A::NO_EFFECT
34    }
35    #[doc = "Pending"]
36    #[inline(always)]
37    pub fn is_pending(&self) -> bool {
38        *self == TRANSMIT_MQ_IRQ_PEND_A::PENDING
39    }
40}
41#[doc = "Field `transmit_mq_irq_pend[0-3]` writer - Transmit Channel\\[i\\] Interrupt Pending"]
42pub type TRANSMIT_MQ_IRQ_PEND_W<'a, REG> = crate::BitWriter1C<'a, REG, TRANSMIT_MQ_IRQ_PEND_A>;
43impl<'a, REG> TRANSMIT_MQ_IRQ_PEND_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "No effect"]
48    #[inline(always)]
49    pub fn no_effect(self) -> &'a mut crate::W<REG> {
50        self.variant(TRANSMIT_MQ_IRQ_PEND_A::NO_EFFECT)
51    }
52    #[doc = "Pending"]
53    #[inline(always)]
54    pub fn pending(self) -> &'a mut crate::W<REG> {
55        self.variant(TRANSMIT_MQ_IRQ_PEND_A::PENDING)
56    }
57}
58impl R {
59    #[doc = "Transmit Channel\\[i\\] Interrupt Pending\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `transmit_mq0_irq_pend` field"]
60    #[inline(always)]
61    pub fn transmit_mq_irq_pend(&self, n: u8) -> TRANSMIT_MQ_IRQ_PEND_R {
62        #[allow(clippy::no_effect)]
63        [(); 4][n as usize];
64        TRANSMIT_MQ_IRQ_PEND_R::new(((self.bits >> (n * 2)) & 1) != 0)
65    }
66    #[doc = "Bit 0 - Transmit Channel\\[i\\] Interrupt Pending"]
67    #[inline(always)]
68    pub fn transmit_mq0_irq_pend(&self) -> TRANSMIT_MQ_IRQ_PEND_R {
69        TRANSMIT_MQ_IRQ_PEND_R::new((self.bits & 1) != 0)
70    }
71    #[doc = "Bit 2 - Transmit Channel\\[i\\] Interrupt Pending"]
72    #[inline(always)]
73    pub fn transmit_mq1_irq_pend(&self) -> TRANSMIT_MQ_IRQ_PEND_R {
74        TRANSMIT_MQ_IRQ_PEND_R::new(((self.bits >> 2) & 1) != 0)
75    }
76    #[doc = "Bit 4 - Transmit Channel\\[i\\] Interrupt Pending"]
77    #[inline(always)]
78    pub fn transmit_mq2_irq_pend(&self) -> TRANSMIT_MQ_IRQ_PEND_R {
79        TRANSMIT_MQ_IRQ_PEND_R::new(((self.bits >> 4) & 1) != 0)
80    }
81    #[doc = "Bit 6 - Transmit Channel\\[i\\] Interrupt Pending"]
82    #[inline(always)]
83    pub fn transmit_mq3_irq_pend(&self) -> TRANSMIT_MQ_IRQ_PEND_R {
84        TRANSMIT_MQ_IRQ_PEND_R::new(((self.bits >> 6) & 1) != 0)
85    }
86}
87impl W {
88    #[doc = "Transmit Channel\\[i\\] Interrupt Pending\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `transmit_mq0_irq_pend` field"]
89    #[inline(always)]
90    #[must_use]
91    pub fn transmit_mq_irq_pend(
92        &mut self,
93        n: u8,
94    ) -> TRANSMIT_MQ_IRQ_PEND_W<MSGBOX_WR_IRQ_STATUS_SPEC> {
95        #[allow(clippy::no_effect)]
96        [(); 4][n as usize];
97        TRANSMIT_MQ_IRQ_PEND_W::new(self, n * 2)
98    }
99    #[doc = "Bit 0 - Transmit Channel\\[i\\] Interrupt Pending"]
100    #[inline(always)]
101    #[must_use]
102    pub fn transmit_mq0_irq_pend(&mut self) -> TRANSMIT_MQ_IRQ_PEND_W<MSGBOX_WR_IRQ_STATUS_SPEC> {
103        TRANSMIT_MQ_IRQ_PEND_W::new(self, 0)
104    }
105    #[doc = "Bit 2 - Transmit Channel\\[i\\] Interrupt Pending"]
106    #[inline(always)]
107    #[must_use]
108    pub fn transmit_mq1_irq_pend(&mut self) -> TRANSMIT_MQ_IRQ_PEND_W<MSGBOX_WR_IRQ_STATUS_SPEC> {
109        TRANSMIT_MQ_IRQ_PEND_W::new(self, 2)
110    }
111    #[doc = "Bit 4 - Transmit Channel\\[i\\] Interrupt Pending"]
112    #[inline(always)]
113    #[must_use]
114    pub fn transmit_mq2_irq_pend(&mut self) -> TRANSMIT_MQ_IRQ_PEND_W<MSGBOX_WR_IRQ_STATUS_SPEC> {
115        TRANSMIT_MQ_IRQ_PEND_W::new(self, 4)
116    }
117    #[doc = "Bit 6 - Transmit Channel\\[i\\] Interrupt Pending"]
118    #[inline(always)]
119    #[must_use]
120    pub fn transmit_mq3_irq_pend(&mut self) -> TRANSMIT_MQ_IRQ_PEND_W<MSGBOX_WR_IRQ_STATUS_SPEC> {
121        TRANSMIT_MQ_IRQ_PEND_W::new(self, 6)
122    }
123    #[doc = r" Writes raw bits to the register."]
124    #[doc = r""]
125    #[doc = r" # Safety"]
126    #[doc = r""]
127    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
128    #[inline(always)]
129    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
130        self.bits = bits;
131        self
132    }
133}
134#[doc = "Message Box Write Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msgbox_wr_irq_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msgbox_wr_irq_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
135pub struct MSGBOX_WR_IRQ_STATUS_SPEC;
136impl crate::RegisterSpec for MSGBOX_WR_IRQ_STATUS_SPEC {
137    type Ux = u32;
138}
139#[doc = "`read()` method returns [`msgbox_wr_irq_status::R`](R) reader structure"]
140impl crate::Readable for MSGBOX_WR_IRQ_STATUS_SPEC {}
141#[doc = "`write(|w| ..)` method takes [`msgbox_wr_irq_status::W`](W) writer structure"]
142impl crate::Writable for MSGBOX_WR_IRQ_STATUS_SPEC {
143    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
144    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x01;
145}
146#[doc = "`reset()` method sets msgbox_wr_irq_status to value 0"]
147impl crate::Resettable for MSGBOX_WR_IRQ_STATUS_SPEC {
148    const RESET_VALUE: Self::Ux = 0;
149}
d1_pac/dsp_msgbox/msgbox/msgbox_wr_irq_status.rs

d1_pac/dsp_msgbox/msgbox/
msgbox_wr_irq_status.rs
