1#[doc = "Register `dmac_sta` reader"]
2pub type R = crate::R<DMAC_STA_SPEC>;
3#[doc = "Field `dma_status[0-15]` reader - DMA Channel\\[15:0\\] Status"]
4pub type DMA_STATUS_R = crate::BitReader<DMA_STATUS_A>;
5#[doc = "DMA Channel\\[15:0\\] Status\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum DMA_STATUS_A {
8 #[doc = "0: `0`"]
9 IDLE = 0,
10 #[doc = "1: `1`"]
11 BUSY = 1,
12}
13impl From<DMA_STATUS_A> for bool {
14 #[inline(always)]
15 fn from(variant: DMA_STATUS_A) -> Self {
16 variant as u8 != 0
17 }
18}
19impl DMA_STATUS_R {
20 #[doc = "Get enumerated values variant"]
21 #[inline(always)]
22 pub const fn variant(&self) -> DMA_STATUS_A {
23 match self.bits {
24 false => DMA_STATUS_A::IDLE,
25 true => DMA_STATUS_A::BUSY,
26 }
27 }
28 #[doc = "`0`"]
29 #[inline(always)]
30 pub fn is_idle(&self) -> bool {
31 *self == DMA_STATUS_A::IDLE
32 }
33 #[doc = "`1`"]
34 #[inline(always)]
35 pub fn is_busy(&self) -> bool {
36 *self == DMA_STATUS_A::BUSY
37 }
38}
39#[doc = "Field `mbus_fifo_status` reader - MBUS FIFO Status"]
40pub type MBUS_FIFO_STATUS_R = crate::BitReader<MBUS_FIFO_STATUS_A>;
41#[doc = "MBUS FIFO Status\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum MBUS_FIFO_STATUS_A {
44 #[doc = "0: `0`"]
45 EMPTY = 0,
46 #[doc = "1: `1`"]
47 NOT_EMPTY = 1,
48}
49impl From<MBUS_FIFO_STATUS_A> for bool {
50 #[inline(always)]
51 fn from(variant: MBUS_FIFO_STATUS_A) -> Self {
52 variant as u8 != 0
53 }
54}
55impl MBUS_FIFO_STATUS_R {
56 #[doc = "Get enumerated values variant"]
57 #[inline(always)]
58 pub const fn variant(&self) -> MBUS_FIFO_STATUS_A {
59 match self.bits {
60 false => MBUS_FIFO_STATUS_A::EMPTY,
61 true => MBUS_FIFO_STATUS_A::NOT_EMPTY,
62 }
63 }
64 #[doc = "`0`"]
65 #[inline(always)]
66 pub fn is_empty(&self) -> bool {
67 *self == MBUS_FIFO_STATUS_A::EMPTY
68 }
69 #[doc = "`1`"]
70 #[inline(always)]
71 pub fn is_not_empty(&self) -> bool {
72 *self == MBUS_FIFO_STATUS_A::NOT_EMPTY
73 }
74}
75impl R {
76 #[doc = "DMA Channel\\[15:0\\] Status\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dma_status0` field"]
77 #[inline(always)]
78 pub fn dma_status(&self, n: u8) -> DMA_STATUS_R {
79 #[allow(clippy::no_effect)]
80 [(); 16][n as usize];
81 DMA_STATUS_R::new(((self.bits >> n) & 1) != 0)
82 }
83 #[doc = "Bit 0 - DMA Channel\\[15:0\\] Status"]
84 #[inline(always)]
85 pub fn dma_status0(&self) -> DMA_STATUS_R {
86 DMA_STATUS_R::new((self.bits & 1) != 0)
87 }
88 #[doc = "Bit 1 - DMA Channel\\[15:0\\] Status"]
89 #[inline(always)]
90 pub fn dma_status1(&self) -> DMA_STATUS_R {
91 DMA_STATUS_R::new(((self.bits >> 1) & 1) != 0)
92 }
93 #[doc = "Bit 2 - DMA Channel\\[15:0\\] Status"]
94 #[inline(always)]
95 pub fn dma_status2(&self) -> DMA_STATUS_R {
96 DMA_STATUS_R::new(((self.bits >> 2) & 1) != 0)
97 }
98 #[doc = "Bit 3 - DMA Channel\\[15:0\\] Status"]
99 #[inline(always)]
100 pub fn dma_status3(&self) -> DMA_STATUS_R {
101 DMA_STATUS_R::new(((self.bits >> 3) & 1) != 0)
102 }
103 #[doc = "Bit 4 - DMA Channel\\[15:0\\] Status"]
104 #[inline(always)]
105 pub fn dma_status4(&self) -> DMA_STATUS_R {
106 DMA_STATUS_R::new(((self.bits >> 4) & 1) != 0)
107 }
108 #[doc = "Bit 5 - DMA Channel\\[15:0\\] Status"]
109 #[inline(always)]
110 pub fn dma_status5(&self) -> DMA_STATUS_R {
111 DMA_STATUS_R::new(((self.bits >> 5) & 1) != 0)
112 }
113 #[doc = "Bit 6 - DMA Channel\\[15:0\\] Status"]
114 #[inline(always)]
115 pub fn dma_status6(&self) -> DMA_STATUS_R {
116 DMA_STATUS_R::new(((self.bits >> 6) & 1) != 0)
117 }
118 #[doc = "Bit 7 - DMA Channel\\[15:0\\] Status"]
119 #[inline(always)]
120 pub fn dma_status7(&self) -> DMA_STATUS_R {
121 DMA_STATUS_R::new(((self.bits >> 7) & 1) != 0)
122 }
123 #[doc = "Bit 8 - DMA Channel\\[15:0\\] Status"]
124 #[inline(always)]
125 pub fn dma_status8(&self) -> DMA_STATUS_R {
126 DMA_STATUS_R::new(((self.bits >> 8) & 1) != 0)
127 }
128 #[doc = "Bit 9 - DMA Channel\\[15:0\\] Status"]
129 #[inline(always)]
130 pub fn dma_status9(&self) -> DMA_STATUS_R {
131 DMA_STATUS_R::new(((self.bits >> 9) & 1) != 0)
132 }
133 #[doc = "Bit 10 - DMA Channel\\[15:0\\] Status"]
134 #[inline(always)]
135 pub fn dma_status10(&self) -> DMA_STATUS_R {
136 DMA_STATUS_R::new(((self.bits >> 10) & 1) != 0)
137 }
138 #[doc = "Bit 11 - DMA Channel\\[15:0\\] Status"]
139 #[inline(always)]
140 pub fn dma_status11(&self) -> DMA_STATUS_R {
141 DMA_STATUS_R::new(((self.bits >> 11) & 1) != 0)
142 }
143 #[doc = "Bit 12 - DMA Channel\\[15:0\\] Status"]
144 #[inline(always)]
145 pub fn dma_status12(&self) -> DMA_STATUS_R {
146 DMA_STATUS_R::new(((self.bits >> 12) & 1) != 0)
147 }
148 #[doc = "Bit 13 - DMA Channel\\[15:0\\] Status"]
149 #[inline(always)]
150 pub fn dma_status13(&self) -> DMA_STATUS_R {
151 DMA_STATUS_R::new(((self.bits >> 13) & 1) != 0)
152 }
153 #[doc = "Bit 14 - DMA Channel\\[15:0\\] Status"]
154 #[inline(always)]
155 pub fn dma_status14(&self) -> DMA_STATUS_R {
156 DMA_STATUS_R::new(((self.bits >> 14) & 1) != 0)
157 }
158 #[doc = "Bit 15 - DMA Channel\\[15:0\\] Status"]
159 #[inline(always)]
160 pub fn dma_status15(&self) -> DMA_STATUS_R {
161 DMA_STATUS_R::new(((self.bits >> 15) & 1) != 0)
162 }
163 #[doc = "Bit 31 - MBUS FIFO Status"]
164 #[inline(always)]
165 pub fn mbus_fifo_status(&self) -> MBUS_FIFO_STATUS_R {
166 MBUS_FIFO_STATUS_R::new(((self.bits >> 31) & 1) != 0)
167 }
168}
169#[doc = "DMAC Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmac_sta::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
170pub struct DMAC_STA_SPEC;
171impl crate::RegisterSpec for DMAC_STA_SPEC {
172 type Ux = u32;
173}
174#[doc = "`read()` method returns [`dmac_sta::R`](R) reader structure"]
175impl crate::Readable for DMAC_STA_SPEC {}
176#[doc = "`reset()` method sets dmac_sta to value 0"]
177impl crate::Resettable for DMAC_STA_SPEC {
178 const RESET_VALUE: Self::Ux = 0;
179}