d1_pac/dmac/
dmac_mode.rs

1#[doc = "Register `dmac_mode%s` reader"]
2pub type R = crate::R<DMAC_MODE_SPEC>;
3#[doc = "Register `dmac_mode%s` writer"]
4pub type W = crate::W<DMAC_MODE_SPEC>;
5#[doc = "Field `dma_src_mode` reader - Source Communication Mode Select"]
6pub type DMA_SRC_MODE_R = crate::BitReader<DMA_SRC_MODE_A>;
7#[doc = "Source Communication Mode Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum DMA_SRC_MODE_A {
10    #[doc = "0: `0`"]
11    WAITING = 0,
12    #[doc = "1: `1`"]
13    HANDSHAKE = 1,
14}
15impl From<DMA_SRC_MODE_A> for bool {
16    #[inline(always)]
17    fn from(variant: DMA_SRC_MODE_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl DMA_SRC_MODE_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> DMA_SRC_MODE_A {
25        match self.bits {
26            false => DMA_SRC_MODE_A::WAITING,
27            true => DMA_SRC_MODE_A::HANDSHAKE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_waiting(&self) -> bool {
33        *self == DMA_SRC_MODE_A::WAITING
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_handshake(&self) -> bool {
38        *self == DMA_SRC_MODE_A::HANDSHAKE
39    }
40}
41#[doc = "Field `dma_src_mode` writer - Source Communication Mode Select"]
42pub type DMA_SRC_MODE_W<'a, REG> = crate::BitWriter<'a, REG, DMA_SRC_MODE_A>;
43impl<'a, REG> DMA_SRC_MODE_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn waiting(self) -> &'a mut crate::W<REG> {
50        self.variant(DMA_SRC_MODE_A::WAITING)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn handshake(self) -> &'a mut crate::W<REG> {
55        self.variant(DMA_SRC_MODE_A::HANDSHAKE)
56    }
57}
58#[doc = "Field `dma_dst_mode` reader - Destination Communication Mode Select"]
59pub type DMA_DST_MODE_R = crate::BitReader<DMA_DST_MODE_A>;
60#[doc = "Destination Communication Mode Select\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum DMA_DST_MODE_A {
63    #[doc = "0: `0`"]
64    WAITING = 0,
65    #[doc = "1: `1`"]
66    HANDSHAKE = 1,
67}
68impl From<DMA_DST_MODE_A> for bool {
69    #[inline(always)]
70    fn from(variant: DMA_DST_MODE_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl DMA_DST_MODE_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> DMA_DST_MODE_A {
78        match self.bits {
79            false => DMA_DST_MODE_A::WAITING,
80            true => DMA_DST_MODE_A::HANDSHAKE,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_waiting(&self) -> bool {
86        *self == DMA_DST_MODE_A::WAITING
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_handshake(&self) -> bool {
91        *self == DMA_DST_MODE_A::HANDSHAKE
92    }
93}
94#[doc = "Field `dma_dst_mode` writer - Destination Communication Mode Select"]
95pub type DMA_DST_MODE_W<'a, REG> = crate::BitWriter<'a, REG, DMA_DST_MODE_A>;
96impl<'a, REG> DMA_DST_MODE_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn waiting(self) -> &'a mut crate::W<REG> {
103        self.variant(DMA_DST_MODE_A::WAITING)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn handshake(self) -> &'a mut crate::W<REG> {
108        self.variant(DMA_DST_MODE_A::HANDSHAKE)
109    }
110}
111impl R {
112    #[doc = "Bit 2 - Source Communication Mode Select"]
113    #[inline(always)]
114    pub fn dma_src_mode(&self) -> DMA_SRC_MODE_R {
115        DMA_SRC_MODE_R::new(((self.bits >> 2) & 1) != 0)
116    }
117    #[doc = "Bit 3 - Destination Communication Mode Select"]
118    #[inline(always)]
119    pub fn dma_dst_mode(&self) -> DMA_DST_MODE_R {
120        DMA_DST_MODE_R::new(((self.bits >> 3) & 1) != 0)
121    }
122}
123impl W {
124    #[doc = "Bit 2 - Source Communication Mode Select"]
125    #[inline(always)]
126    #[must_use]
127    pub fn dma_src_mode(&mut self) -> DMA_SRC_MODE_W<DMAC_MODE_SPEC> {
128        DMA_SRC_MODE_W::new(self, 2)
129    }
130    #[doc = "Bit 3 - Destination Communication Mode Select"]
131    #[inline(always)]
132    #[must_use]
133    pub fn dma_dst_mode(&mut self) -> DMA_DST_MODE_W<DMAC_MODE_SPEC> {
134        DMA_DST_MODE_W::new(self, 3)
135    }
136    #[doc = r" Writes raw bits to the register."]
137    #[doc = r""]
138    #[doc = r" # Safety"]
139    #[doc = r""]
140    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
141    #[inline(always)]
142    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
143        self.bits = bits;
144        self
145    }
146}
147#[doc = "DMAC Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmac_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmac_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
148pub struct DMAC_MODE_SPEC;
149impl crate::RegisterSpec for DMAC_MODE_SPEC {
150    type Ux = u32;
151}
152#[doc = "`read()` method returns [`dmac_mode::R`](R) reader structure"]
153impl crate::Readable for DMAC_MODE_SPEC {}
154#[doc = "`write(|w| ..)` method takes [`dmac_mode::W`](W) writer structure"]
155impl crate::Writable for DMAC_MODE_SPEC {
156    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
157    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
158}
159#[doc = "`reset()` method sets dmac_mode%s to value 0"]
160impl crate::Resettable for DMAC_MODE_SPEC {
161    const RESET_VALUE: Self::Ux = 0;
162}
d1_pac/dmac/dmac_mode.rs

d1_pac/dmac/
dmac_mode.rs
