d1_pac/dmac/
dmac_irq_en1.rs

1#[doc = "Register `dmac_irq_en1` reader"]
2pub type R = crate::R<DMAC_IRQ_EN1_SPEC>;
3#[doc = "Register `dmac_irq_en1` writer"]
4pub type W = crate::W<DMAC_IRQ_EN1_SPEC>;
5#[doc = "Field `dma_hlaf_irq_en[8-15]` reader - Enable the half package interrupt of DMA"]
6pub type DMA_HLAF_IRQ_EN_R = crate::BitReader<DMA_HLAF_IRQ_EN_A>;
7#[doc = "Enable the half package interrupt of DMA\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum DMA_HLAF_IRQ_EN_A {
10    #[doc = "0: `0`"]
11    DISABLED = 0,
12    #[doc = "1: `1`"]
13    ENABLED = 1,
14}
15impl From<DMA_HLAF_IRQ_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: DMA_HLAF_IRQ_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl DMA_HLAF_IRQ_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> DMA_HLAF_IRQ_EN_A {
25        match self.bits {
26            false => DMA_HLAF_IRQ_EN_A::DISABLED,
27            true => DMA_HLAF_IRQ_EN_A::ENABLED,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disabled(&self) -> bool {
33        *self == DMA_HLAF_IRQ_EN_A::DISABLED
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enabled(&self) -> bool {
38        *self == DMA_HLAF_IRQ_EN_A::ENABLED
39    }
40}
41#[doc = "Field `dma_hlaf_irq_en[8-15]` writer - Enable the half package interrupt of DMA"]
42pub type DMA_HLAF_IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, DMA_HLAF_IRQ_EN_A>;
43impl<'a, REG> DMA_HLAF_IRQ_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disabled(self) -> &'a mut crate::W<REG> {
50        self.variant(DMA_HLAF_IRQ_EN_A::DISABLED)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enabled(self) -> &'a mut crate::W<REG> {
55        self.variant(DMA_HLAF_IRQ_EN_A::ENABLED)
56    }
57}
58#[doc = "Field `dma_pkg_irq_en[8-15]` reader - Enable the package end interrupt of DMA"]
59pub type DMA_PKG_IRQ_EN_R = crate::BitReader<DMA_PKG_IRQ_EN_A>;
60#[doc = "Enable the package end interrupt of DMA\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum DMA_PKG_IRQ_EN_A {
63    #[doc = "0: `0`"]
64    DISABLED = 0,
65    #[doc = "1: `1`"]
66    ENABLED = 1,
67}
68impl From<DMA_PKG_IRQ_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: DMA_PKG_IRQ_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl DMA_PKG_IRQ_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> DMA_PKG_IRQ_EN_A {
78        match self.bits {
79            false => DMA_PKG_IRQ_EN_A::DISABLED,
80            true => DMA_PKG_IRQ_EN_A::ENABLED,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_disabled(&self) -> bool {
86        *self == DMA_PKG_IRQ_EN_A::DISABLED
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_enabled(&self) -> bool {
91        *self == DMA_PKG_IRQ_EN_A::ENABLED
92    }
93}
94#[doc = "Field `dma_pkg_irq_en[8-15]` writer - Enable the package end interrupt of DMA"]
95pub type DMA_PKG_IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, DMA_PKG_IRQ_EN_A>;
96impl<'a, REG> DMA_PKG_IRQ_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn disabled(self) -> &'a mut crate::W<REG> {
103        self.variant(DMA_PKG_IRQ_EN_A::DISABLED)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn enabled(self) -> &'a mut crate::W<REG> {
108        self.variant(DMA_PKG_IRQ_EN_A::ENABLED)
109    }
110}
111#[doc = "Field `dma_queue_irq_en[8-15]` reader - Enable the queue end interrupt of DMA"]
112pub type DMA_QUEUE_IRQ_EN_R = crate::BitReader<DMA_QUEUE_IRQ_EN_A>;
113#[doc = "Enable the queue end interrupt of DMA\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum DMA_QUEUE_IRQ_EN_A {
116    #[doc = "0: `0`"]
117    DISABLED = 0,
118    #[doc = "1: `1`"]
119    ENABLED = 1,
120}
121impl From<DMA_QUEUE_IRQ_EN_A> for bool {
122    #[inline(always)]
123    fn from(variant: DMA_QUEUE_IRQ_EN_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl DMA_QUEUE_IRQ_EN_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> DMA_QUEUE_IRQ_EN_A {
131        match self.bits {
132            false => DMA_QUEUE_IRQ_EN_A::DISABLED,
133            true => DMA_QUEUE_IRQ_EN_A::ENABLED,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_disabled(&self) -> bool {
139        *self == DMA_QUEUE_IRQ_EN_A::DISABLED
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_enabled(&self) -> bool {
144        *self == DMA_QUEUE_IRQ_EN_A::ENABLED
145    }
146}
147#[doc = "Field `dma_queue_irq_en[8-15]` writer - Enable the queue end interrupt of DMA"]
148pub type DMA_QUEUE_IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, DMA_QUEUE_IRQ_EN_A>;
149impl<'a, REG> DMA_QUEUE_IRQ_EN_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn disabled(self) -> &'a mut crate::W<REG> {
156        self.variant(DMA_QUEUE_IRQ_EN_A::DISABLED)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn enabled(self) -> &'a mut crate::W<REG> {
161        self.variant(DMA_QUEUE_IRQ_EN_A::ENABLED)
162    }
163}
164impl R {
165    #[doc = "Enable the half package interrupt of DMA\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dma8_hlaf_irq_en` field"]
166    #[inline(always)]
167    pub fn dma_hlaf_irq_en(&self, n: u8) -> DMA_HLAF_IRQ_EN_R {
168        #[allow(clippy::no_effect)]
169        [(); 8][n as usize];
170        DMA_HLAF_IRQ_EN_R::new(((self.bits >> (n * 4)) & 1) != 0)
171    }
172    #[doc = "Bit 0 - Enable the half package interrupt of DMA"]
173    #[inline(always)]
174    pub fn dma8_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
175        DMA_HLAF_IRQ_EN_R::new((self.bits & 1) != 0)
176    }
177    #[doc = "Bit 4 - Enable the half package interrupt of DMA"]
178    #[inline(always)]
179    pub fn dma9_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
180        DMA_HLAF_IRQ_EN_R::new(((self.bits >> 4) & 1) != 0)
181    }
182    #[doc = "Bit 8 - Enable the half package interrupt of DMA"]
183    #[inline(always)]
184    pub fn dma10_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
185        DMA_HLAF_IRQ_EN_R::new(((self.bits >> 8) & 1) != 0)
186    }
187    #[doc = "Bit 12 - Enable the half package interrupt of DMA"]
188    #[inline(always)]
189    pub fn dma11_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
190        DMA_HLAF_IRQ_EN_R::new(((self.bits >> 12) & 1) != 0)
191    }
192    #[doc = "Bit 16 - Enable the half package interrupt of DMA"]
193    #[inline(always)]
194    pub fn dma12_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
195        DMA_HLAF_IRQ_EN_R::new(((self.bits >> 16) & 1) != 0)
196    }
197    #[doc = "Bit 20 - Enable the half package interrupt of DMA"]
198    #[inline(always)]
199    pub fn dma13_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
200        DMA_HLAF_IRQ_EN_R::new(((self.bits >> 20) & 1) != 0)
201    }
202    #[doc = "Bit 24 - Enable the half package interrupt of DMA"]
203    #[inline(always)]
204    pub fn dma14_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
205        DMA_HLAF_IRQ_EN_R::new(((self.bits >> 24) & 1) != 0)
206    }
207    #[doc = "Bit 28 - Enable the half package interrupt of DMA"]
208    #[inline(always)]
209    pub fn dma15_hlaf_irq_en(&self) -> DMA_HLAF_IRQ_EN_R {
210        DMA_HLAF_IRQ_EN_R::new(((self.bits >> 28) & 1) != 0)
211    }
212    #[doc = "Enable the package end interrupt of DMA\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dma8_pkg_irq_en` field"]
213    #[inline(always)]
214    pub fn dma_pkg_irq_en(&self, n: u8) -> DMA_PKG_IRQ_EN_R {
215        #[allow(clippy::no_effect)]
216        [(); 8][n as usize];
217        DMA_PKG_IRQ_EN_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0)
218    }
219    #[doc = "Bit 1 - Enable the package end interrupt of DMA"]
220    #[inline(always)]
221    pub fn dma8_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
222        DMA_PKG_IRQ_EN_R::new(((self.bits >> 1) & 1) != 0)
223    }
224    #[doc = "Bit 5 - Enable the package end interrupt of DMA"]
225    #[inline(always)]
226    pub fn dma9_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
227        DMA_PKG_IRQ_EN_R::new(((self.bits >> 5) & 1) != 0)
228    }
229    #[doc = "Bit 9 - Enable the package end interrupt of DMA"]
230    #[inline(always)]
231    pub fn dma10_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
232        DMA_PKG_IRQ_EN_R::new(((self.bits >> 9) & 1) != 0)
233    }
234    #[doc = "Bit 13 - Enable the package end interrupt of DMA"]
235    #[inline(always)]
236    pub fn dma11_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
237        DMA_PKG_IRQ_EN_R::new(((self.bits >> 13) & 1) != 0)
238    }
239    #[doc = "Bit 17 - Enable the package end interrupt of DMA"]
240    #[inline(always)]
241    pub fn dma12_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
242        DMA_PKG_IRQ_EN_R::new(((self.bits >> 17) & 1) != 0)
243    }
244    #[doc = "Bit 21 - Enable the package end interrupt of DMA"]
245    #[inline(always)]
246    pub fn dma13_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
247        DMA_PKG_IRQ_EN_R::new(((self.bits >> 21) & 1) != 0)
248    }
249    #[doc = "Bit 25 - Enable the package end interrupt of DMA"]
250    #[inline(always)]
251    pub fn dma14_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
252        DMA_PKG_IRQ_EN_R::new(((self.bits >> 25) & 1) != 0)
253    }
254    #[doc = "Bit 29 - Enable the package end interrupt of DMA"]
255    #[inline(always)]
256    pub fn dma15_pkg_irq_en(&self) -> DMA_PKG_IRQ_EN_R {
257        DMA_PKG_IRQ_EN_R::new(((self.bits >> 29) & 1) != 0)
258    }
259    #[doc = "Enable the queue end interrupt of DMA\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dma8_queue_irq_en` field"]
260    #[inline(always)]
261    pub fn dma_queue_irq_en(&self, n: u8) -> DMA_QUEUE_IRQ_EN_R {
262        #[allow(clippy::no_effect)]
263        [(); 8][n as usize];
264        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> (n * 4 + 2)) & 1) != 0)
265    }
266    #[doc = "Bit 2 - Enable the queue end interrupt of DMA"]
267    #[inline(always)]
268    pub fn dma8_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
269        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 2) & 1) != 0)
270    }
271    #[doc = "Bit 6 - Enable the queue end interrupt of DMA"]
272    #[inline(always)]
273    pub fn dma9_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
274        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 6) & 1) != 0)
275    }
276    #[doc = "Bit 10 - Enable the queue end interrupt of DMA"]
277    #[inline(always)]
278    pub fn dma10_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
279        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 10) & 1) != 0)
280    }
281    #[doc = "Bit 14 - Enable the queue end interrupt of DMA"]
282    #[inline(always)]
283    pub fn dma11_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
284        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 14) & 1) != 0)
285    }
286    #[doc = "Bit 18 - Enable the queue end interrupt of DMA"]
287    #[inline(always)]
288    pub fn dma12_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
289        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 18) & 1) != 0)
290    }
291    #[doc = "Bit 22 - Enable the queue end interrupt of DMA"]
292    #[inline(always)]
293    pub fn dma13_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
294        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 22) & 1) != 0)
295    }
296    #[doc = "Bit 26 - Enable the queue end interrupt of DMA"]
297    #[inline(always)]
298    pub fn dma14_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
299        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 26) & 1) != 0)
300    }
301    #[doc = "Bit 30 - Enable the queue end interrupt of DMA"]
302    #[inline(always)]
303    pub fn dma15_queue_irq_en(&self) -> DMA_QUEUE_IRQ_EN_R {
304        DMA_QUEUE_IRQ_EN_R::new(((self.bits >> 30) & 1) != 0)
305    }
306}
307impl W {
308    #[doc = "Enable the half package interrupt of DMA\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dma8_hlaf_irq_en` field"]
309    #[inline(always)]
310    #[must_use]
311    pub fn dma_hlaf_irq_en(&mut self, n: u8) -> DMA_HLAF_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
312        #[allow(clippy::no_effect)]
313        [(); 8][n as usize];
314        DMA_HLAF_IRQ_EN_W::new(self, n * 4)
315    }
316    #[doc = "Bit 0 - Enable the half package interrupt of DMA"]
317    #[inline(always)]
318    #[must_use]
319    pub fn dma8_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
320        DMA_HLAF_IRQ_EN_W::new(self, 0)
321    }
322    #[doc = "Bit 4 - Enable the half package interrupt of DMA"]
323    #[inline(always)]
324    #[must_use]
325    pub fn dma9_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
326        DMA_HLAF_IRQ_EN_W::new(self, 4)
327    }
328    #[doc = "Bit 8 - Enable the half package interrupt of DMA"]
329    #[inline(always)]
330    #[must_use]
331    pub fn dma10_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
332        DMA_HLAF_IRQ_EN_W::new(self, 8)
333    }
334    #[doc = "Bit 12 - Enable the half package interrupt of DMA"]
335    #[inline(always)]
336    #[must_use]
337    pub fn dma11_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
338        DMA_HLAF_IRQ_EN_W::new(self, 12)
339    }
340    #[doc = "Bit 16 - Enable the half package interrupt of DMA"]
341    #[inline(always)]
342    #[must_use]
343    pub fn dma12_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
344        DMA_HLAF_IRQ_EN_W::new(self, 16)
345    }
346    #[doc = "Bit 20 - Enable the half package interrupt of DMA"]
347    #[inline(always)]
348    #[must_use]
349    pub fn dma13_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
350        DMA_HLAF_IRQ_EN_W::new(self, 20)
351    }
352    #[doc = "Bit 24 - Enable the half package interrupt of DMA"]
353    #[inline(always)]
354    #[must_use]
355    pub fn dma14_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
356        DMA_HLAF_IRQ_EN_W::new(self, 24)
357    }
358    #[doc = "Bit 28 - Enable the half package interrupt of DMA"]
359    #[inline(always)]
360    #[must_use]
361    pub fn dma15_hlaf_irq_en(&mut self) -> DMA_HLAF_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
362        DMA_HLAF_IRQ_EN_W::new(self, 28)
363    }
364    #[doc = "Enable the package end interrupt of DMA\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dma8_pkg_irq_en` field"]
365    #[inline(always)]
366    #[must_use]
367    pub fn dma_pkg_irq_en(&mut self, n: u8) -> DMA_PKG_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
368        #[allow(clippy::no_effect)]
369        [(); 8][n as usize];
370        DMA_PKG_IRQ_EN_W::new(self, n * 4 + 1)
371    }
372    #[doc = "Bit 1 - Enable the package end interrupt of DMA"]
373    #[inline(always)]
374    #[must_use]
375    pub fn dma8_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
376        DMA_PKG_IRQ_EN_W::new(self, 1)
377    }
378    #[doc = "Bit 5 - Enable the package end interrupt of DMA"]
379    #[inline(always)]
380    #[must_use]
381    pub fn dma9_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
382        DMA_PKG_IRQ_EN_W::new(self, 5)
383    }
384    #[doc = "Bit 9 - Enable the package end interrupt of DMA"]
385    #[inline(always)]
386    #[must_use]
387    pub fn dma10_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
388        DMA_PKG_IRQ_EN_W::new(self, 9)
389    }
390    #[doc = "Bit 13 - Enable the package end interrupt of DMA"]
391    #[inline(always)]
392    #[must_use]
393    pub fn dma11_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
394        DMA_PKG_IRQ_EN_W::new(self, 13)
395    }
396    #[doc = "Bit 17 - Enable the package end interrupt of DMA"]
397    #[inline(always)]
398    #[must_use]
399    pub fn dma12_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
400        DMA_PKG_IRQ_EN_W::new(self, 17)
401    }
402    #[doc = "Bit 21 - Enable the package end interrupt of DMA"]
403    #[inline(always)]
404    #[must_use]
405    pub fn dma13_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
406        DMA_PKG_IRQ_EN_W::new(self, 21)
407    }
408    #[doc = "Bit 25 - Enable the package end interrupt of DMA"]
409    #[inline(always)]
410    #[must_use]
411    pub fn dma14_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
412        DMA_PKG_IRQ_EN_W::new(self, 25)
413    }
414    #[doc = "Bit 29 - Enable the package end interrupt of DMA"]
415    #[inline(always)]
416    #[must_use]
417    pub fn dma15_pkg_irq_en(&mut self) -> DMA_PKG_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
418        DMA_PKG_IRQ_EN_W::new(self, 29)
419    }
420    #[doc = "Enable the queue end interrupt of DMA\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dma8_queue_irq_en` field"]
421    #[inline(always)]
422    #[must_use]
423    pub fn dma_queue_irq_en(&mut self, n: u8) -> DMA_QUEUE_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
424        #[allow(clippy::no_effect)]
425        [(); 8][n as usize];
426        DMA_QUEUE_IRQ_EN_W::new(self, n * 4 + 2)
427    }
428    #[doc = "Bit 2 - Enable the queue end interrupt of DMA"]
429    #[inline(always)]
430    #[must_use]
431    pub fn dma8_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
432        DMA_QUEUE_IRQ_EN_W::new(self, 2)
433    }
434    #[doc = "Bit 6 - Enable the queue end interrupt of DMA"]
435    #[inline(always)]
436    #[must_use]
437    pub fn dma9_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
438        DMA_QUEUE_IRQ_EN_W::new(self, 6)
439    }
440    #[doc = "Bit 10 - Enable the queue end interrupt of DMA"]
441    #[inline(always)]
442    #[must_use]
443    pub fn dma10_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
444        DMA_QUEUE_IRQ_EN_W::new(self, 10)
445    }
446    #[doc = "Bit 14 - Enable the queue end interrupt of DMA"]
447    #[inline(always)]
448    #[must_use]
449    pub fn dma11_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
450        DMA_QUEUE_IRQ_EN_W::new(self, 14)
451    }
452    #[doc = "Bit 18 - Enable the queue end interrupt of DMA"]
453    #[inline(always)]
454    #[must_use]
455    pub fn dma12_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
456        DMA_QUEUE_IRQ_EN_W::new(self, 18)
457    }
458    #[doc = "Bit 22 - Enable the queue end interrupt of DMA"]
459    #[inline(always)]
460    #[must_use]
461    pub fn dma13_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
462        DMA_QUEUE_IRQ_EN_W::new(self, 22)
463    }
464    #[doc = "Bit 26 - Enable the queue end interrupt of DMA"]
465    #[inline(always)]
466    #[must_use]
467    pub fn dma14_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
468        DMA_QUEUE_IRQ_EN_W::new(self, 26)
469    }
470    #[doc = "Bit 30 - Enable the queue end interrupt of DMA"]
471    #[inline(always)]
472    #[must_use]
473    pub fn dma15_queue_irq_en(&mut self) -> DMA_QUEUE_IRQ_EN_W<DMAC_IRQ_EN1_SPEC> {
474        DMA_QUEUE_IRQ_EN_W::new(self, 30)
475    }
476    #[doc = r" Writes raw bits to the register."]
477    #[doc = r""]
478    #[doc = r" # Safety"]
479    #[doc = r""]
480    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
481    #[inline(always)]
482    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
483        self.bits = bits;
484        self
485    }
486}
487#[doc = "DMAC IRQ Enable Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmac_irq_en1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmac_irq_en1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
488pub struct DMAC_IRQ_EN1_SPEC;
489impl crate::RegisterSpec for DMAC_IRQ_EN1_SPEC {
490    type Ux = u32;
491}
492#[doc = "`read()` method returns [`dmac_irq_en1::R`](R) reader structure"]
493impl crate::Readable for DMAC_IRQ_EN1_SPEC {}
494#[doc = "`write(|w| ..)` method takes [`dmac_irq_en1::W`](W) writer structure"]
495impl crate::Writable for DMAC_IRQ_EN1_SPEC {
496    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
497    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
498}
499#[doc = "`reset()` method sets dmac_irq_en1 to value 0"]
500impl crate::Resettable for DMAC_IRQ_EN1_SPEC {
501    const RESET_VALUE: Self::Ux = 0;
502}
d1_pac/dmac/dmac_irq_en1.rs

d1_pac/dmac/
dmac_irq_en1.rs
