d1_pac/dmac/
dmac_desc_addr.rs

1#[doc = "Register `dmac_desc_addr%s` reader"]
2pub type R = crate::R<DMAC_DESC_ADDR_SPEC>;
3#[doc = "Register `dmac_desc_addr%s` writer"]
4pub type W = crate::W<DMAC_DESC_ADDR_SPEC>;
5#[doc = "Field `dma_desc_high_addr` reader - Higher 2 bits of DMA channel descriptor high address\n\nDMA Channel Descriptor Address = {bit\\[1:0\\], bit\\[31:2\\], 2'b00}"]
6pub type DMA_DESC_HIGH_ADDR_R = crate::FieldReader;
7#[doc = "Field `dma_desc_high_addr` writer - Higher 2 bits of DMA channel descriptor high address\n\nDMA Channel Descriptor Address = {bit\\[1:0\\], bit\\[31:2\\], 2'b00}"]
8pub type DMA_DESC_HIGH_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `dma_desc_addr` reader - Lower 30 bits of DMA channel descriptor address"]
10pub type DMA_DESC_ADDR_R = crate::FieldReader<u32>;
11#[doc = "Field `dma_desc_addr` writer - Lower 30 bits of DMA channel descriptor address"]
12pub type DMA_DESC_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 30, u32>;
13impl R {
14    #[doc = "Bits 0:1 - Higher 2 bits of DMA channel descriptor high address\n\nDMA Channel Descriptor Address = {bit\\[1:0\\], bit\\[31:2\\], 2'b00}"]
15    #[inline(always)]
16    pub fn dma_desc_high_addr(&self) -> DMA_DESC_HIGH_ADDR_R {
17        DMA_DESC_HIGH_ADDR_R::new((self.bits & 3) as u8)
18    }
19    #[doc = "Bits 2:31 - Lower 30 bits of DMA channel descriptor address"]
20    #[inline(always)]
21    pub fn dma_desc_addr(&self) -> DMA_DESC_ADDR_R {
22        DMA_DESC_ADDR_R::new((self.bits >> 2) & 0x3fff_ffff)
23    }
24}
25impl W {
26    #[doc = "Bits 0:1 - Higher 2 bits of DMA channel descriptor high address\n\nDMA Channel Descriptor Address = {bit\\[1:0\\], bit\\[31:2\\], 2'b00}"]
27    #[inline(always)]
28    #[must_use]
29    pub fn dma_desc_high_addr(&mut self) -> DMA_DESC_HIGH_ADDR_W<DMAC_DESC_ADDR_SPEC> {
30        DMA_DESC_HIGH_ADDR_W::new(self, 0)
31    }
32    #[doc = "Bits 2:31 - Lower 30 bits of DMA channel descriptor address"]
33    #[inline(always)]
34    #[must_use]
35    pub fn dma_desc_addr(&mut self) -> DMA_DESC_ADDR_W<DMAC_DESC_ADDR_SPEC> {
36        DMA_DESC_ADDR_W::new(self, 2)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "DMAC Channel Start Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmac_desc_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmac_desc_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
50pub struct DMAC_DESC_ADDR_SPEC;
51impl crate::RegisterSpec for DMAC_DESC_ADDR_SPEC {
52    type Ux = u32;
53}
54#[doc = "`read()` method returns [`dmac_desc_addr::R`](R) reader structure"]
55impl crate::Readable for DMAC_DESC_ADDR_SPEC {}
56#[doc = "`write(|w| ..)` method takes [`dmac_desc_addr::W`](W) writer structure"]
57impl crate::Writable for DMAC_DESC_ADDR_SPEC {
58    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
59    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
60}
61#[doc = "`reset()` method sets dmac_desc_addr%s to value 0"]
62impl crate::Resettable for DMAC_DESC_ADDR_SPEC {
63    const RESET_VALUE: Self::Ux = 0;
64}
d1_pac/dmac/dmac_desc_addr.rs

d1_pac/dmac/
dmac_desc_addr.rs
