d1_pac/csic/csic_top/
csic_ptn_ctrl.rs

1#[doc = "Register `csic_ptn_ctrl` reader"]
2pub type R = crate::R<CSIC_PTN_CTRL_SPEC>;
3#[doc = "Register `csic_ptn_ctrl` writer"]
4pub type W = crate::W<CSIC_PTN_CTRL_SPEC>;
5#[doc = "Field `ptn_gen_dly` reader - Clocks delayed before pattern generating start."]
6pub type PTN_GEN_DLY_R = crate::FieldReader;
7#[doc = "Field `ptn_gen_dly` writer - Clocks delayed before pattern generating start."]
8pub type PTN_GEN_DLY_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `ptn_gen_clk_div` reader - Packet generator clock divider"]
10pub type PTN_GEN_CLK_DIV_R = crate::FieldReader;
11#[doc = "Field `ptn_gen_clk_div` writer - Packet generator clock divider"]
12pub type PTN_GEN_CLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `ptn_mode` reader - Pattern mode selection"]
14pub type PTN_MODE_R = crate::FieldReader<PTN_MODE_A>;
15#[doc = "Pattern mode selection\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17#[repr(u8)]
18pub enum PTN_MODE_A {
19    #[doc = "4: `100`"]
20    NCSIC_YUV_8BIT = 4,
21    #[doc = "5: `101`"]
22    NCSIC_YUV_16BIT = 5,
23    #[doc = "9: `1001`"]
24    BT656_8BIT = 9,
25    #[doc = "10: `1010`"]
26    BT656_16BIT = 10,
27    #[doc = "13: `1101`"]
28    BAYER_12BIT = 13,
29    #[doc = "14: `1110`"]
30    UYVY422_12BIT = 14,
31    #[doc = "15: `1111`"]
32    UYVY420_12BIT = 15,
33}
34impl From<PTN_MODE_A> for u8 {
35    #[inline(always)]
36    fn from(variant: PTN_MODE_A) -> Self {
37        variant as _
38    }
39}
40impl crate::FieldSpec for PTN_MODE_A {
41    type Ux = u8;
42}
43impl PTN_MODE_R {
44    #[doc = "Get enumerated values variant"]
45    #[inline(always)]
46    pub const fn variant(&self) -> Option<PTN_MODE_A> {
47        match self.bits {
48            4 => Some(PTN_MODE_A::NCSIC_YUV_8BIT),
49            5 => Some(PTN_MODE_A::NCSIC_YUV_16BIT),
50            9 => Some(PTN_MODE_A::BT656_8BIT),
51            10 => Some(PTN_MODE_A::BT656_16BIT),
52            13 => Some(PTN_MODE_A::BAYER_12BIT),
53            14 => Some(PTN_MODE_A::UYVY422_12BIT),
54            15 => Some(PTN_MODE_A::UYVY420_12BIT),
55            _ => None,
56        }
57    }
58    #[doc = "`100`"]
59    #[inline(always)]
60    pub fn is_ncsic_yuv_8bit(&self) -> bool {
61        *self == PTN_MODE_A::NCSIC_YUV_8BIT
62    }
63    #[doc = "`101`"]
64    #[inline(always)]
65    pub fn is_ncsic_yuv_16bit(&self) -> bool {
66        *self == PTN_MODE_A::NCSIC_YUV_16BIT
67    }
68    #[doc = "`1001`"]
69    #[inline(always)]
70    pub fn is_bt656_8bit(&self) -> bool {
71        *self == PTN_MODE_A::BT656_8BIT
72    }
73    #[doc = "`1010`"]
74    #[inline(always)]
75    pub fn is_bt656_16bit(&self) -> bool {
76        *self == PTN_MODE_A::BT656_16BIT
77    }
78    #[doc = "`1101`"]
79    #[inline(always)]
80    pub fn is_bayer_12bit(&self) -> bool {
81        *self == PTN_MODE_A::BAYER_12BIT
82    }
83    #[doc = "`1110`"]
84    #[inline(always)]
85    pub fn is_uyvy422_12bit(&self) -> bool {
86        *self == PTN_MODE_A::UYVY422_12BIT
87    }
88    #[doc = "`1111`"]
89    #[inline(always)]
90    pub fn is_uyvy420_12bit(&self) -> bool {
91        *self == PTN_MODE_A::UYVY420_12BIT
92    }
93}
94#[doc = "Field `ptn_mode` writer - Pattern mode selection"]
95pub type PTN_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PTN_MODE_A>;
96impl<'a, REG> PTN_MODE_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99    REG::Ux: From<u8>,
100{
101    #[doc = "`100`"]
102    #[inline(always)]
103    pub fn ncsic_yuv_8bit(self) -> &'a mut crate::W<REG> {
104        self.variant(PTN_MODE_A::NCSIC_YUV_8BIT)
105    }
106    #[doc = "`101`"]
107    #[inline(always)]
108    pub fn ncsic_yuv_16bit(self) -> &'a mut crate::W<REG> {
109        self.variant(PTN_MODE_A::NCSIC_YUV_16BIT)
110    }
111    #[doc = "`1001`"]
112    #[inline(always)]
113    pub fn bt656_8bit(self) -> &'a mut crate::W<REG> {
114        self.variant(PTN_MODE_A::BT656_8BIT)
115    }
116    #[doc = "`1010`"]
117    #[inline(always)]
118    pub fn bt656_16bit(self) -> &'a mut crate::W<REG> {
119        self.variant(PTN_MODE_A::BT656_16BIT)
120    }
121    #[doc = "`1101`"]
122    #[inline(always)]
123    pub fn bayer_12bit(self) -> &'a mut crate::W<REG> {
124        self.variant(PTN_MODE_A::BAYER_12BIT)
125    }
126    #[doc = "`1110`"]
127    #[inline(always)]
128    pub fn uyvy422_12bit(self) -> &'a mut crate::W<REG> {
129        self.variant(PTN_MODE_A::UYVY422_12BIT)
130    }
131    #[doc = "`1111`"]
132    #[inline(always)]
133    pub fn uyvy420_12bit(self) -> &'a mut crate::W<REG> {
134        self.variant(PTN_MODE_A::UYVY420_12BIT)
135    }
136}
137#[doc = "Field `ptn_gen_data_width` reader - "]
138pub type PTN_GEN_DATA_WIDTH_R = crate::FieldReader<PTN_GEN_DATA_WIDTH_A>;
139#[doc = "\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141#[repr(u8)]
142pub enum PTN_GEN_DATA_WIDTH_A {
143    #[doc = "0: `0`"]
144    _8BIT = 0,
145    #[doc = "1: `1`"]
146    _10BIT = 1,
147    #[doc = "2: `10`"]
148    _12BIT = 2,
149}
150impl From<PTN_GEN_DATA_WIDTH_A> for u8 {
151    #[inline(always)]
152    fn from(variant: PTN_GEN_DATA_WIDTH_A) -> Self {
153        variant as _
154    }
155}
156impl crate::FieldSpec for PTN_GEN_DATA_WIDTH_A {
157    type Ux = u8;
158}
159impl PTN_GEN_DATA_WIDTH_R {
160    #[doc = "Get enumerated values variant"]
161    #[inline(always)]
162    pub const fn variant(&self) -> Option<PTN_GEN_DATA_WIDTH_A> {
163        match self.bits {
164            0 => Some(PTN_GEN_DATA_WIDTH_A::_8BIT),
165            1 => Some(PTN_GEN_DATA_WIDTH_A::_10BIT),
166            2 => Some(PTN_GEN_DATA_WIDTH_A::_12BIT),
167            _ => None,
168        }
169    }
170    #[doc = "`0`"]
171    #[inline(always)]
172    pub fn is_8bit(&self) -> bool {
173        *self == PTN_GEN_DATA_WIDTH_A::_8BIT
174    }
175    #[doc = "`1`"]
176    #[inline(always)]
177    pub fn is_10bit(&self) -> bool {
178        *self == PTN_GEN_DATA_WIDTH_A::_10BIT
179    }
180    #[doc = "`10`"]
181    #[inline(always)]
182    pub fn is_12bit(&self) -> bool {
183        *self == PTN_GEN_DATA_WIDTH_A::_12BIT
184    }
185}
186#[doc = "Field `ptn_gen_data_width` writer - "]
187pub type PTN_GEN_DATA_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PTN_GEN_DATA_WIDTH_A>;
188impl<'a, REG> PTN_GEN_DATA_WIDTH_W<'a, REG>
189where
190    REG: crate::Writable + crate::RegisterSpec,
191    REG::Ux: From<u8>,
192{
193    #[doc = "`0`"]
194    #[inline(always)]
195    pub fn _8bit(self) -> &'a mut crate::W<REG> {
196        self.variant(PTN_GEN_DATA_WIDTH_A::_8BIT)
197    }
198    #[doc = "`1`"]
199    #[inline(always)]
200    pub fn _10bit(self) -> &'a mut crate::W<REG> {
201        self.variant(PTN_GEN_DATA_WIDTH_A::_10BIT)
202    }
203    #[doc = "`10`"]
204    #[inline(always)]
205    pub fn _12bit(self) -> &'a mut crate::W<REG> {
206        self.variant(PTN_GEN_DATA_WIDTH_A::_12BIT)
207    }
208}
209#[doc = "Field `ptn_port_sel` reader - Pattern Generator output port selection"]
210pub type PTN_PORT_SEL_R = crate::FieldReader<PTN_PORT_SEL_A>;
211#[doc = "Pattern Generator output port selection\n\nValue on reset: 0"]
212#[derive(Clone, Copy, Debug, PartialEq, Eq)]
213#[repr(u8)]
214pub enum PTN_PORT_SEL_A {
215    #[doc = "2: `10`"]
216    NSCIC0 = 2,
217}
218impl From<PTN_PORT_SEL_A> for u8 {
219    #[inline(always)]
220    fn from(variant: PTN_PORT_SEL_A) -> Self {
221        variant as _
222    }
223}
224impl crate::FieldSpec for PTN_PORT_SEL_A {
225    type Ux = u8;
226}
227impl PTN_PORT_SEL_R {
228    #[doc = "Get enumerated values variant"]
229    #[inline(always)]
230    pub const fn variant(&self) -> Option<PTN_PORT_SEL_A> {
231        match self.bits {
232            2 => Some(PTN_PORT_SEL_A::NSCIC0),
233            _ => None,
234        }
235    }
236    #[doc = "`10`"]
237    #[inline(always)]
238    pub fn is_nscic0(&self) -> bool {
239        *self == PTN_PORT_SEL_A::NSCIC0
240    }
241}
242#[doc = "Field `ptn_port_sel` writer - Pattern Generator output port selection"]
243pub type PTN_PORT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PTN_PORT_SEL_A>;
244impl<'a, REG> PTN_PORT_SEL_W<'a, REG>
245where
246    REG: crate::Writable + crate::RegisterSpec,
247    REG::Ux: From<u8>,
248{
249    #[doc = "`10`"]
250    #[inline(always)]
251    pub fn nscic0(self) -> &'a mut crate::W<REG> {
252        self.variant(PTN_PORT_SEL_A::NSCIC0)
253    }
254}
255impl R {
256    #[doc = "Bits 0:7 - Clocks delayed before pattern generating start."]
257    #[inline(always)]
258    pub fn ptn_gen_dly(&self) -> PTN_GEN_DLY_R {
259        PTN_GEN_DLY_R::new((self.bits & 0xff) as u8)
260    }
261    #[doc = "Bits 8:9 - Packet generator clock divider"]
262    #[inline(always)]
263    pub fn ptn_gen_clk_div(&self) -> PTN_GEN_CLK_DIV_R {
264        PTN_GEN_CLK_DIV_R::new(((self.bits >> 8) & 3) as u8)
265    }
266    #[doc = "Bits 16:19 - Pattern mode selection"]
267    #[inline(always)]
268    pub fn ptn_mode(&self) -> PTN_MODE_R {
269        PTN_MODE_R::new(((self.bits >> 16) & 0x0f) as u8)
270    }
271    #[doc = "Bits 20:21"]
272    #[inline(always)]
273    pub fn ptn_gen_data_width(&self) -> PTN_GEN_DATA_WIDTH_R {
274        PTN_GEN_DATA_WIDTH_R::new(((self.bits >> 20) & 3) as u8)
275    }
276    #[doc = "Bits 24:25 - Pattern Generator output port selection"]
277    #[inline(always)]
278    pub fn ptn_port_sel(&self) -> PTN_PORT_SEL_R {
279        PTN_PORT_SEL_R::new(((self.bits >> 24) & 3) as u8)
280    }
281}
282impl W {
283    #[doc = "Bits 0:7 - Clocks delayed before pattern generating start."]
284    #[inline(always)]
285    #[must_use]
286    pub fn ptn_gen_dly(&mut self) -> PTN_GEN_DLY_W<CSIC_PTN_CTRL_SPEC> {
287        PTN_GEN_DLY_W::new(self, 0)
288    }
289    #[doc = "Bits 8:9 - Packet generator clock divider"]
290    #[inline(always)]
291    #[must_use]
292    pub fn ptn_gen_clk_div(&mut self) -> PTN_GEN_CLK_DIV_W<CSIC_PTN_CTRL_SPEC> {
293        PTN_GEN_CLK_DIV_W::new(self, 8)
294    }
295    #[doc = "Bits 16:19 - Pattern mode selection"]
296    #[inline(always)]
297    #[must_use]
298    pub fn ptn_mode(&mut self) -> PTN_MODE_W<CSIC_PTN_CTRL_SPEC> {
299        PTN_MODE_W::new(self, 16)
300    }
301    #[doc = "Bits 20:21"]
302    #[inline(always)]
303    #[must_use]
304    pub fn ptn_gen_data_width(&mut self) -> PTN_GEN_DATA_WIDTH_W<CSIC_PTN_CTRL_SPEC> {
305        PTN_GEN_DATA_WIDTH_W::new(self, 20)
306    }
307    #[doc = "Bits 24:25 - Pattern Generator output port selection"]
308    #[inline(always)]
309    #[must_use]
310    pub fn ptn_port_sel(&mut self) -> PTN_PORT_SEL_W<CSIC_PTN_CTRL_SPEC> {
311        PTN_PORT_SEL_W::new(self, 24)
312    }
313    #[doc = r" Writes raw bits to the register."]
314    #[doc = r""]
315    #[doc = r" # Safety"]
316    #[doc = r""]
317    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
318    #[inline(always)]
319    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
320        self.bits = bits;
321        self
322    }
323}
324#[doc = "CSIC Pattern Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csic_ptn_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csic_ptn_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
325pub struct CSIC_PTN_CTRL_SPEC;
326impl crate::RegisterSpec for CSIC_PTN_CTRL_SPEC {
327    type Ux = u32;
328}
329#[doc = "`read()` method returns [`csic_ptn_ctrl::R`](R) reader structure"]
330impl crate::Readable for CSIC_PTN_CTRL_SPEC {}
331#[doc = "`write(|w| ..)` method takes [`csic_ptn_ctrl::W`](W) writer structure"]
332impl crate::Writable for CSIC_PTN_CTRL_SPEC {
333    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
334    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
335}
336#[doc = "`reset()` method sets csic_ptn_ctrl to value 0x0f"]
337impl crate::Resettable for CSIC_PTN_CTRL_SPEC {
338    const RESET_VALUE: Self::Ux = 0x0f;
339}
d1_pac/csic/csic_top/csic_ptn_ctrl.rs

d1_pac/csic/csic_top/
csic_ptn_ctrl.rs
