d1_pac/csic/csic_top/
csic_dma_input_sel.rs

1#[doc = "Register `csic_dma%s_input_sel` reader"]
2pub type R = crate::R<CSIC_DMA_INPUT_SEL_SPEC>;
3#[doc = "Register `csic_dma%s_input_sel` writer"]
4pub type W = crate::W<CSIC_DMA_INPUT_SEL_SPEC>;
5#[doc = "Field `input_sel` reader - Input selection for DMA\\[i\\]"]
6pub type INPUT_SEL_R = crate::FieldReader<INPUT_SEL_A>;
7#[doc = "Input selection for DMA\\[i\\]\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum INPUT_SEL_A {
11    #[doc = "0: `0`"]
12    ISP0_CH0 = 0,
13    #[doc = "1: `1`"]
14    ISP0_CH1 = 1,
15    #[doc = "2: `10`"]
16    ISP0_CH2 = 2,
17    #[doc = "3: `11`"]
18    ISP0_CH3 = 3,
19}
20impl From<INPUT_SEL_A> for u8 {
21    #[inline(always)]
22    fn from(variant: INPUT_SEL_A) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for INPUT_SEL_A {
27    type Ux = u8;
28}
29impl INPUT_SEL_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> Option<INPUT_SEL_A> {
33        match self.bits {
34            0 => Some(INPUT_SEL_A::ISP0_CH0),
35            1 => Some(INPUT_SEL_A::ISP0_CH1),
36            2 => Some(INPUT_SEL_A::ISP0_CH2),
37            3 => Some(INPUT_SEL_A::ISP0_CH3),
38            _ => None,
39        }
40    }
41    #[doc = "`0`"]
42    #[inline(always)]
43    pub fn is_isp0_ch0(&self) -> bool {
44        *self == INPUT_SEL_A::ISP0_CH0
45    }
46    #[doc = "`1`"]
47    #[inline(always)]
48    pub fn is_isp0_ch1(&self) -> bool {
49        *self == INPUT_SEL_A::ISP0_CH1
50    }
51    #[doc = "`10`"]
52    #[inline(always)]
53    pub fn is_isp0_ch2(&self) -> bool {
54        *self == INPUT_SEL_A::ISP0_CH2
55    }
56    #[doc = "`11`"]
57    #[inline(always)]
58    pub fn is_isp0_ch3(&self) -> bool {
59        *self == INPUT_SEL_A::ISP0_CH3
60    }
61}
62#[doc = "Field `input_sel` writer - Input selection for DMA\\[i\\]"]
63pub type INPUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4, INPUT_SEL_A>;
64impl<'a, REG> INPUT_SEL_W<'a, REG>
65where
66    REG: crate::Writable + crate::RegisterSpec,
67    REG::Ux: From<u8>,
68{
69    #[doc = "`0`"]
70    #[inline(always)]
71    pub fn isp0_ch0(self) -> &'a mut crate::W<REG> {
72        self.variant(INPUT_SEL_A::ISP0_CH0)
73    }
74    #[doc = "`1`"]
75    #[inline(always)]
76    pub fn isp0_ch1(self) -> &'a mut crate::W<REG> {
77        self.variant(INPUT_SEL_A::ISP0_CH1)
78    }
79    #[doc = "`10`"]
80    #[inline(always)]
81    pub fn isp0_ch2(self) -> &'a mut crate::W<REG> {
82        self.variant(INPUT_SEL_A::ISP0_CH2)
83    }
84    #[doc = "`11`"]
85    #[inline(always)]
86    pub fn isp0_ch3(self) -> &'a mut crate::W<REG> {
87        self.variant(INPUT_SEL_A::ISP0_CH3)
88    }
89}
90impl R {
91    #[doc = "Bits 0:3 - Input selection for DMA\\[i\\]"]
92    #[inline(always)]
93    pub fn input_sel(&self) -> INPUT_SEL_R {
94        INPUT_SEL_R::new((self.bits & 0x0f) as u8)
95    }
96}
97impl W {
98    #[doc = "Bits 0:3 - Input selection for DMA\\[i\\]"]
99    #[inline(always)]
100    #[must_use]
101    pub fn input_sel(&mut self) -> INPUT_SEL_W<CSIC_DMA_INPUT_SEL_SPEC> {
102        INPUT_SEL_W::new(self, 0)
103    }
104    #[doc = r" Writes raw bits to the register."]
105    #[doc = r""]
106    #[doc = r" # Safety"]
107    #[doc = r""]
108    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
109    #[inline(always)]
110    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
111        self.bits = bits;
112        self
113    }
114}
115#[doc = "CSIC DMA\\[i\\] Input Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csic_dma_input_sel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csic_dma_input_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
116pub struct CSIC_DMA_INPUT_SEL_SPEC;
117impl crate::RegisterSpec for CSIC_DMA_INPUT_SEL_SPEC {
118    type Ux = u32;
119}
120#[doc = "`read()` method returns [`csic_dma_input_sel::R`](R) reader structure"]
121impl crate::Readable for CSIC_DMA_INPUT_SEL_SPEC {}
122#[doc = "`write(|w| ..)` method takes [`csic_dma_input_sel::W`](W) writer structure"]
123impl crate::Writable for CSIC_DMA_INPUT_SEL_SPEC {
124    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
125    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
126}
127#[doc = "`reset()` method sets csic_dma%s_input_sel to value 0"]
128impl crate::Resettable for CSIC_DMA_INPUT_SEL_SPEC {
129    const RESET_VALUE: Self::Ux = 0;
130}
d1_pac/csic/csic_top/csic_dma_input_sel.rs

d1_pac/csic/csic_top/
csic_dma_input_sel.rs
