d1_pac/csic/csic_top/
csic_bist_control.rs

1#[doc = "Register `csic_bist_control` reader"]
2pub type R = crate::R<CSIC_BIST_CONTROL_SPEC>;
3#[doc = "Register `csic_bist_control` writer"]
4pub type W = crate::W<CSIC_BIST_CONTROL_SPEC>;
5#[doc = "Field `bist_en` reader - BIST enable\n\nA positive will trigger the BIST to start."]
6pub type BIST_EN_R = crate::BitReader;
7#[doc = "Field `bist_en` writer - BIST enable\n\nA positive will trigger the BIST to start."]
8pub type BIST_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `bist_wdata_pat` reader - BIST write data pattern"]
10pub type BIST_WDATA_PAT_R = crate::FieldReader<BIST_WDATA_PAT_A>;
11#[doc = "BIST write data pattern\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum BIST_WDATA_PAT_A {
15    #[doc = "0: `0`"]
16    _0X00000000 = 0,
17    #[doc = "1: `1`"]
18    _0X55555555 = 1,
19    #[doc = "2: `10`"]
20    _0X33333333 = 2,
21    #[doc = "3: `11`"]
22    _0X0F0F0F0F = 3,
23    #[doc = "4: `100`"]
24    _0X00FF00FF = 4,
25    #[doc = "5: `101`"]
26    _0X0000FFFF = 5,
27}
28impl From<BIST_WDATA_PAT_A> for u8 {
29    #[inline(always)]
30    fn from(variant: BIST_WDATA_PAT_A) -> Self {
31        variant as _
32    }
33}
34impl crate::FieldSpec for BIST_WDATA_PAT_A {
35    type Ux = u8;
36}
37impl BIST_WDATA_PAT_R {
38    #[doc = "Get enumerated values variant"]
39    #[inline(always)]
40    pub const fn variant(&self) -> Option<BIST_WDATA_PAT_A> {
41        match self.bits {
42            0 => Some(BIST_WDATA_PAT_A::_0X00000000),
43            1 => Some(BIST_WDATA_PAT_A::_0X55555555),
44            2 => Some(BIST_WDATA_PAT_A::_0X33333333),
45            3 => Some(BIST_WDATA_PAT_A::_0X0F0F0F0F),
46            4 => Some(BIST_WDATA_PAT_A::_0X00FF00FF),
47            5 => Some(BIST_WDATA_PAT_A::_0X0000FFFF),
48            _ => None,
49        }
50    }
51    #[doc = "`0`"]
52    #[inline(always)]
53    pub fn is_0x00000000(&self) -> bool {
54        *self == BIST_WDATA_PAT_A::_0X00000000
55    }
56    #[doc = "`1`"]
57    #[inline(always)]
58    pub fn is_0x55555555(&self) -> bool {
59        *self == BIST_WDATA_PAT_A::_0X55555555
60    }
61    #[doc = "`10`"]
62    #[inline(always)]
63    pub fn is_0x33333333(&self) -> bool {
64        *self == BIST_WDATA_PAT_A::_0X33333333
65    }
66    #[doc = "`11`"]
67    #[inline(always)]
68    pub fn is_0x0f0f0f0f(&self) -> bool {
69        *self == BIST_WDATA_PAT_A::_0X0F0F0F0F
70    }
71    #[doc = "`100`"]
72    #[inline(always)]
73    pub fn is_0x00ff00ff(&self) -> bool {
74        *self == BIST_WDATA_PAT_A::_0X00FF00FF
75    }
76    #[doc = "`101`"]
77    #[inline(always)]
78    pub fn is_0x0000ffff(&self) -> bool {
79        *self == BIST_WDATA_PAT_A::_0X0000FFFF
80    }
81}
82#[doc = "Field `bist_wdata_pat` writer - BIST write data pattern"]
83pub type BIST_WDATA_PAT_W<'a, REG> = crate::FieldWriter<'a, REG, 3, BIST_WDATA_PAT_A>;
84impl<'a, REG> BIST_WDATA_PAT_W<'a, REG>
85where
86    REG: crate::Writable + crate::RegisterSpec,
87    REG::Ux: From<u8>,
88{
89    #[doc = "`0`"]
90    #[inline(always)]
91    pub fn _0x00000000(self) -> &'a mut crate::W<REG> {
92        self.variant(BIST_WDATA_PAT_A::_0X00000000)
93    }
94    #[doc = "`1`"]
95    #[inline(always)]
96    pub fn _0x55555555(self) -> &'a mut crate::W<REG> {
97        self.variant(BIST_WDATA_PAT_A::_0X55555555)
98    }
99    #[doc = "`10`"]
100    #[inline(always)]
101    pub fn _0x33333333(self) -> &'a mut crate::W<REG> {
102        self.variant(BIST_WDATA_PAT_A::_0X33333333)
103    }
104    #[doc = "`11`"]
105    #[inline(always)]
106    pub fn _0x0f0f0f0f(self) -> &'a mut crate::W<REG> {
107        self.variant(BIST_WDATA_PAT_A::_0X0F0F0F0F)
108    }
109    #[doc = "`100`"]
110    #[inline(always)]
111    pub fn _0x00ff00ff(self) -> &'a mut crate::W<REG> {
112        self.variant(BIST_WDATA_PAT_A::_0X00FF00FF)
113    }
114    #[doc = "`101`"]
115    #[inline(always)]
116    pub fn _0x0000ffff(self) -> &'a mut crate::W<REG> {
117        self.variant(BIST_WDATA_PAT_A::_0X0000FFFF)
118    }
119}
120#[doc = "Field `bist_addr_mode_sel` reader - BIST address mode select"]
121pub type BIST_ADDR_MODE_SEL_R = crate::BitReader;
122#[doc = "Field `bist_addr_mode_sel` writer - BIST address mode select"]
123pub type BIST_ADDR_MODE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
124#[doc = "Field `bist_reg_sel` reader - BIST register select"]
125pub type BIST_REG_SEL_R = crate::FieldReader;
126#[doc = "Field `bist_reg_sel` writer - BIST register select"]
127pub type BIST_REG_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
128#[doc = "Field `bist_busy` reader - BIST busy"]
129pub type BIST_BUSY_R = crate::BitReader<BIST_BUSY_A>;
130#[doc = "BIST busy\n\nValue on reset: 0"]
131#[derive(Clone, Copy, Debug, PartialEq, Eq)]
132pub enum BIST_BUSY_A {
133    #[doc = "0: `0`"]
134    IDLE = 0,
135    #[doc = "1: `1`"]
136    BUSY = 1,
137}
138impl From<BIST_BUSY_A> for bool {
139    #[inline(always)]
140    fn from(variant: BIST_BUSY_A) -> Self {
141        variant as u8 != 0
142    }
143}
144impl BIST_BUSY_R {
145    #[doc = "Get enumerated values variant"]
146    #[inline(always)]
147    pub const fn variant(&self) -> BIST_BUSY_A {
148        match self.bits {
149            false => BIST_BUSY_A::IDLE,
150            true => BIST_BUSY_A::BUSY,
151        }
152    }
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn is_idle(&self) -> bool {
156        *self == BIST_BUSY_A::IDLE
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn is_busy(&self) -> bool {
161        *self == BIST_BUSY_A::BUSY
162    }
163}
164#[doc = "Field `bist_stop` reader - BIST stop"]
165pub type BIST_STOP_R = crate::BitReader<BIST_STOP_A>;
166#[doc = "BIST stop\n\nValue on reset: 1"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum BIST_STOP_A {
169    #[doc = "0: `0`"]
170    RUNNING = 0,
171    #[doc = "1: `1`"]
172    STOP = 1,
173}
174impl From<BIST_STOP_A> for bool {
175    #[inline(always)]
176    fn from(variant: BIST_STOP_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl BIST_STOP_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> BIST_STOP_A {
184        match self.bits {
185            false => BIST_STOP_A::RUNNING,
186            true => BIST_STOP_A::STOP,
187        }
188    }
189    #[doc = "`0`"]
190    #[inline(always)]
191    pub fn is_running(&self) -> bool {
192        *self == BIST_STOP_A::RUNNING
193    }
194    #[doc = "`1`"]
195    #[inline(always)]
196    pub fn is_stop(&self) -> bool {
197        *self == BIST_STOP_A::STOP
198    }
199}
200#[doc = "Field `bist_err_cyc` reader - BIST error cycle"]
201pub type BIST_ERR_CYC_R = crate::FieldReader;
202#[doc = "Field `bist_err_pat` reader - BIST error pattern"]
203pub type BIST_ERR_PAT_R = crate::FieldReader;
204#[doc = "Field `bist_err_sta` reader - BIST error status"]
205pub type BIST_ERR_STA_R = crate::BitReader<BIST_ERR_STA_A>;
206#[doc = "BIST error status\n\nValue on reset: 0"]
207#[derive(Clone, Copy, Debug, PartialEq, Eq)]
208pub enum BIST_ERR_STA_A {
209    #[doc = "0: `0`"]
210    NO_EFFECT = 0,
211    #[doc = "1: `1`"]
212    ERROR = 1,
213}
214impl From<BIST_ERR_STA_A> for bool {
215    #[inline(always)]
216    fn from(variant: BIST_ERR_STA_A) -> Self {
217        variant as u8 != 0
218    }
219}
220impl BIST_ERR_STA_R {
221    #[doc = "Get enumerated values variant"]
222    #[inline(always)]
223    pub const fn variant(&self) -> BIST_ERR_STA_A {
224        match self.bits {
225            false => BIST_ERR_STA_A::NO_EFFECT,
226            true => BIST_ERR_STA_A::ERROR,
227        }
228    }
229    #[doc = "`0`"]
230    #[inline(always)]
231    pub fn is_no_effect(&self) -> bool {
232        *self == BIST_ERR_STA_A::NO_EFFECT
233    }
234    #[doc = "`1`"]
235    #[inline(always)]
236    pub fn is_error(&self) -> bool {
237        *self == BIST_ERR_STA_A::ERROR
238    }
239}
240impl R {
241    #[doc = "Bit 0 - BIST enable\n\nA positive will trigger the BIST to start."]
242    #[inline(always)]
243    pub fn bist_en(&self) -> BIST_EN_R {
244        BIST_EN_R::new((self.bits & 1) != 0)
245    }
246    #[doc = "Bits 1:3 - BIST write data pattern"]
247    #[inline(always)]
248    pub fn bist_wdata_pat(&self) -> BIST_WDATA_PAT_R {
249        BIST_WDATA_PAT_R::new(((self.bits >> 1) & 7) as u8)
250    }
251    #[doc = "Bit 4 - BIST address mode select"]
252    #[inline(always)]
253    pub fn bist_addr_mode_sel(&self) -> BIST_ADDR_MODE_SEL_R {
254        BIST_ADDR_MODE_SEL_R::new(((self.bits >> 4) & 1) != 0)
255    }
256    #[doc = "Bits 5:7 - BIST register select"]
257    #[inline(always)]
258    pub fn bist_reg_sel(&self) -> BIST_REG_SEL_R {
259        BIST_REG_SEL_R::new(((self.bits >> 5) & 7) as u8)
260    }
261    #[doc = "Bit 8 - BIST busy"]
262    #[inline(always)]
263    pub fn bist_busy(&self) -> BIST_BUSY_R {
264        BIST_BUSY_R::new(((self.bits >> 8) & 1) != 0)
265    }
266    #[doc = "Bit 9 - BIST stop"]
267    #[inline(always)]
268    pub fn bist_stop(&self) -> BIST_STOP_R {
269        BIST_STOP_R::new(((self.bits >> 9) & 1) != 0)
270    }
271    #[doc = "Bits 10:11 - BIST error cycle"]
272    #[inline(always)]
273    pub fn bist_err_cyc(&self) -> BIST_ERR_CYC_R {
274        BIST_ERR_CYC_R::new(((self.bits >> 10) & 3) as u8)
275    }
276    #[doc = "Bits 12:14 - BIST error pattern"]
277    #[inline(always)]
278    pub fn bist_err_pat(&self) -> BIST_ERR_PAT_R {
279        BIST_ERR_PAT_R::new(((self.bits >> 12) & 7) as u8)
280    }
281    #[doc = "Bit 15 - BIST error status"]
282    #[inline(always)]
283    pub fn bist_err_sta(&self) -> BIST_ERR_STA_R {
284        BIST_ERR_STA_R::new(((self.bits >> 15) & 1) != 0)
285    }
286}
287impl W {
288    #[doc = "Bit 0 - BIST enable\n\nA positive will trigger the BIST to start."]
289    #[inline(always)]
290    #[must_use]
291    pub fn bist_en(&mut self) -> BIST_EN_W<CSIC_BIST_CONTROL_SPEC> {
292        BIST_EN_W::new(self, 0)
293    }
294    #[doc = "Bits 1:3 - BIST write data pattern"]
295    #[inline(always)]
296    #[must_use]
297    pub fn bist_wdata_pat(&mut self) -> BIST_WDATA_PAT_W<CSIC_BIST_CONTROL_SPEC> {
298        BIST_WDATA_PAT_W::new(self, 1)
299    }
300    #[doc = "Bit 4 - BIST address mode select"]
301    #[inline(always)]
302    #[must_use]
303    pub fn bist_addr_mode_sel(&mut self) -> BIST_ADDR_MODE_SEL_W<CSIC_BIST_CONTROL_SPEC> {
304        BIST_ADDR_MODE_SEL_W::new(self, 4)
305    }
306    #[doc = "Bits 5:7 - BIST register select"]
307    #[inline(always)]
308    #[must_use]
309    pub fn bist_reg_sel(&mut self) -> BIST_REG_SEL_W<CSIC_BIST_CONTROL_SPEC> {
310        BIST_REG_SEL_W::new(self, 5)
311    }
312    #[doc = r" Writes raw bits to the register."]
313    #[doc = r""]
314    #[doc = r" # Safety"]
315    #[doc = r""]
316    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
317    #[inline(always)]
318    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
319        self.bits = bits;
320        self
321    }
322}
323#[doc = "CSIC BIST Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csic_bist_control::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csic_bist_control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
324pub struct CSIC_BIST_CONTROL_SPEC;
325impl crate::RegisterSpec for CSIC_BIST_CONTROL_SPEC {
326    type Ux = u32;
327}
328#[doc = "`read()` method returns [`csic_bist_control::R`](R) reader structure"]
329impl crate::Readable for CSIC_BIST_CONTROL_SPEC {}
330#[doc = "`write(|w| ..)` method takes [`csic_bist_control::W`](W) writer structure"]
331impl crate::Writable for CSIC_BIST_CONTROL_SPEC {
332    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
333    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
334}
335#[doc = "`reset()` method sets csic_bist_control to value 0x0200"]
336impl crate::Resettable for CSIC_BIST_CONTROL_SPEC {
337    const RESET_VALUE: Self::Ux = 0x0200;
338}
d1_pac/csic/csic_top/csic_bist_control.rs

d1_pac/csic/csic_top/
csic_bist_control.rs
