d1_pac/csic/csic_parser0/
prs_ncsic_if_cfg.rs

1#[doc = "Register `prs_ncsic_if_cfg` reader"]
2pub type R = crate::R<PRS_NCSIC_IF_CFG_SPEC>;
3#[doc = "Register `prs_ncsic_if_cfg` writer"]
4pub type W = crate::W<PRS_NCSIC_IF_CFG_SPEC>;
5#[doc = "Field `csi_if` reader - "]
6pub type CSI_IF_R = crate::FieldReader<CSI_IF_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum CSI_IF_A {
11    #[doc = "0: RAW or YUV420/YUYV422 (each cycle one component input)"]
12    RAW_YUV420_YUYV422 = 0,
13    #[doc = "4: BT656 1 channel"]
14    BT656_1CH = 4,
15    #[doc = "12: BT656 2 channel (All data interleaved in one data bus)"]
16    BT656_2CH = 12,
17    #[doc = "14: BT656 4 channel (All data interleaved in one data bus)"]
18    BT656_4CH = 14,
19}
20impl From<CSI_IF_A> for u8 {
21    #[inline(always)]
22    fn from(variant: CSI_IF_A) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for CSI_IF_A {
27    type Ux = u8;
28}
29impl CSI_IF_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> Option<CSI_IF_A> {
33        match self.bits {
34            0 => Some(CSI_IF_A::RAW_YUV420_YUYV422),
35            4 => Some(CSI_IF_A::BT656_1CH),
36            12 => Some(CSI_IF_A::BT656_2CH),
37            14 => Some(CSI_IF_A::BT656_4CH),
38            _ => None,
39        }
40    }
41    #[doc = "RAW or YUV420/YUYV422 (each cycle one component input)"]
42    #[inline(always)]
43    pub fn is_raw_yuv420_yuyv422(&self) -> bool {
44        *self == CSI_IF_A::RAW_YUV420_YUYV422
45    }
46    #[doc = "BT656 1 channel"]
47    #[inline(always)]
48    pub fn is_bt656_1ch(&self) -> bool {
49        *self == CSI_IF_A::BT656_1CH
50    }
51    #[doc = "BT656 2 channel (All data interleaved in one data bus)"]
52    #[inline(always)]
53    pub fn is_bt656_2ch(&self) -> bool {
54        *self == CSI_IF_A::BT656_2CH
55    }
56    #[doc = "BT656 4 channel (All data interleaved in one data bus)"]
57    #[inline(always)]
58    pub fn is_bt656_4ch(&self) -> bool {
59        *self == CSI_IF_A::BT656_4CH
60    }
61}
62#[doc = "Field `csi_if` writer - "]
63pub type CSI_IF_W<'a, REG> = crate::FieldWriter<'a, REG, 5, CSI_IF_A>;
64impl<'a, REG> CSI_IF_W<'a, REG>
65where
66    REG: crate::Writable + crate::RegisterSpec,
67    REG::Ux: From<u8>,
68{
69    #[doc = "RAW or YUV420/YUYV422 (each cycle one component input)"]
70    #[inline(always)]
71    pub fn raw_yuv420_yuyv422(self) -> &'a mut crate::W<REG> {
72        self.variant(CSI_IF_A::RAW_YUV420_YUYV422)
73    }
74    #[doc = "BT656 1 channel"]
75    #[inline(always)]
76    pub fn bt656_1ch(self) -> &'a mut crate::W<REG> {
77        self.variant(CSI_IF_A::BT656_1CH)
78    }
79    #[doc = "BT656 2 channel (All data interleaved in one data bus)"]
80    #[inline(always)]
81    pub fn bt656_2ch(self) -> &'a mut crate::W<REG> {
82        self.variant(CSI_IF_A::BT656_2CH)
83    }
84    #[doc = "BT656 4 channel (All data interleaved in one data bus)"]
85    #[inline(always)]
86    pub fn bt656_4ch(self) -> &'a mut crate::W<REG> {
87        self.variant(CSI_IF_A::BT656_4CH)
88    }
89}
90#[doc = "Field `input_seq` reader - Input data sequence, only valid for YUV422 and YUV420 input format"]
91pub type INPUT_SEQ_R = crate::FieldReader<INPUT_SEQ_A>;
92#[doc = "Input data sequence, only valid for YUV422 and YUV420 input format\n\nValue on reset: 2"]
93#[derive(Clone, Copy, Debug, PartialEq, Eq)]
94#[repr(u8)]
95pub enum INPUT_SEQ_A {
96    #[doc = "0: `0`"]
97    YUYV = 0,
98    #[doc = "1: `1`"]
99    YVYU = 1,
100    #[doc = "2: `10`"]
101    UYVY = 2,
102    #[doc = "3: `11`"]
103    VYUY = 3,
104}
105impl From<INPUT_SEQ_A> for u8 {
106    #[inline(always)]
107    fn from(variant: INPUT_SEQ_A) -> Self {
108        variant as _
109    }
110}
111impl crate::FieldSpec for INPUT_SEQ_A {
112    type Ux = u8;
113}
114impl INPUT_SEQ_R {
115    #[doc = "Get enumerated values variant"]
116    #[inline(always)]
117    pub const fn variant(&self) -> INPUT_SEQ_A {
118        match self.bits {
119            0 => INPUT_SEQ_A::YUYV,
120            1 => INPUT_SEQ_A::YVYU,
121            2 => INPUT_SEQ_A::UYVY,
122            3 => INPUT_SEQ_A::VYUY,
123            _ => unreachable!(),
124        }
125    }
126    #[doc = "`0`"]
127    #[inline(always)]
128    pub fn is_yuyv(&self) -> bool {
129        *self == INPUT_SEQ_A::YUYV
130    }
131    #[doc = "`1`"]
132    #[inline(always)]
133    pub fn is_yvyu(&self) -> bool {
134        *self == INPUT_SEQ_A::YVYU
135    }
136    #[doc = "`10`"]
137    #[inline(always)]
138    pub fn is_uyvy(&self) -> bool {
139        *self == INPUT_SEQ_A::UYVY
140    }
141    #[doc = "`11`"]
142    #[inline(always)]
143    pub fn is_vyuy(&self) -> bool {
144        *self == INPUT_SEQ_A::VYUY
145    }
146}
147#[doc = "Field `input_seq` writer - Input data sequence, only valid for YUV422 and YUV420 input format"]
148pub type INPUT_SEQ_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, INPUT_SEQ_A>;
149impl<'a, REG> INPUT_SEQ_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152    REG::Ux: From<u8>,
153{
154    #[doc = "`0`"]
155    #[inline(always)]
156    pub fn yuyv(self) -> &'a mut crate::W<REG> {
157        self.variant(INPUT_SEQ_A::YUYV)
158    }
159    #[doc = "`1`"]
160    #[inline(always)]
161    pub fn yvyu(self) -> &'a mut crate::W<REG> {
162        self.variant(INPUT_SEQ_A::YVYU)
163    }
164    #[doc = "`10`"]
165    #[inline(always)]
166    pub fn uyvy(self) -> &'a mut crate::W<REG> {
167        self.variant(INPUT_SEQ_A::UYVY)
168    }
169    #[doc = "`11`"]
170    #[inline(always)]
171    pub fn vyuy(self) -> &'a mut crate::W<REG> {
172        self.variant(INPUT_SEQ_A::VYUY)
173    }
174}
175#[doc = "Field `if_data_width` reader - "]
176pub type IF_DATA_WIDTH_R = crate::FieldReader<IF_DATA_WIDTH_A>;
177#[doc = "\n\nValue on reset: 0"]
178#[derive(Clone, Copy, Debug, PartialEq, Eq)]
179#[repr(u8)]
180pub enum IF_DATA_WIDTH_A {
181    #[doc = "0: 8 bit data bus"]
182    _8BIT = 0,
183    #[doc = "1: 10 bit data bus"]
184    _10BIT = 1,
185    #[doc = "2: 12 bit data bus"]
186    _12BIT = 2,
187    #[doc = "3: 8 + 2 bit data bus"]
188    _8P2BIT = 3,
189    #[doc = "4: 2 * 8 bit data bus"]
190    _2X8BIT = 4,
191}
192impl From<IF_DATA_WIDTH_A> for u8 {
193    #[inline(always)]
194    fn from(variant: IF_DATA_WIDTH_A) -> Self {
195        variant as _
196    }
197}
198impl crate::FieldSpec for IF_DATA_WIDTH_A {
199    type Ux = u8;
200}
201impl IF_DATA_WIDTH_R {
202    #[doc = "Get enumerated values variant"]
203    #[inline(always)]
204    pub const fn variant(&self) -> Option<IF_DATA_WIDTH_A> {
205        match self.bits {
206            0 => Some(IF_DATA_WIDTH_A::_8BIT),
207            1 => Some(IF_DATA_WIDTH_A::_10BIT),
208            2 => Some(IF_DATA_WIDTH_A::_12BIT),
209            3 => Some(IF_DATA_WIDTH_A::_8P2BIT),
210            4 => Some(IF_DATA_WIDTH_A::_2X8BIT),
211            _ => None,
212        }
213    }
214    #[doc = "8 bit data bus"]
215    #[inline(always)]
216    pub fn is_8bit(&self) -> bool {
217        *self == IF_DATA_WIDTH_A::_8BIT
218    }
219    #[doc = "10 bit data bus"]
220    #[inline(always)]
221    pub fn is_10bit(&self) -> bool {
222        *self == IF_DATA_WIDTH_A::_10BIT
223    }
224    #[doc = "12 bit data bus"]
225    #[inline(always)]
226    pub fn is_12bit(&self) -> bool {
227        *self == IF_DATA_WIDTH_A::_12BIT
228    }
229    #[doc = "8 + 2 bit data bus"]
230    #[inline(always)]
231    pub fn is_8p2bit(&self) -> bool {
232        *self == IF_DATA_WIDTH_A::_8P2BIT
233    }
234    #[doc = "2 * 8 bit data bus"]
235    #[inline(always)]
236    pub fn is_2x8bit(&self) -> bool {
237        *self == IF_DATA_WIDTH_A::_2X8BIT
238    }
239}
240#[doc = "Field `if_data_width` writer - "]
241pub type IF_DATA_WIDTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3, IF_DATA_WIDTH_A>;
242impl<'a, REG> IF_DATA_WIDTH_W<'a, REG>
243where
244    REG: crate::Writable + crate::RegisterSpec,
245    REG::Ux: From<u8>,
246{
247    #[doc = "8 bit data bus"]
248    #[inline(always)]
249    pub fn _8bit(self) -> &'a mut crate::W<REG> {
250        self.variant(IF_DATA_WIDTH_A::_8BIT)
251    }
252    #[doc = "10 bit data bus"]
253    #[inline(always)]
254    pub fn _10bit(self) -> &'a mut crate::W<REG> {
255        self.variant(IF_DATA_WIDTH_A::_10BIT)
256    }
257    #[doc = "12 bit data bus"]
258    #[inline(always)]
259    pub fn _12bit(self) -> &'a mut crate::W<REG> {
260        self.variant(IF_DATA_WIDTH_A::_12BIT)
261    }
262    #[doc = "8 + 2 bit data bus"]
263    #[inline(always)]
264    pub fn _8p2bit(self) -> &'a mut crate::W<REG> {
265        self.variant(IF_DATA_WIDTH_A::_8P2BIT)
266    }
267    #[doc = "2 * 8 bit data bus"]
268    #[inline(always)]
269    pub fn _2x8bit(self) -> &'a mut crate::W<REG> {
270        self.variant(IF_DATA_WIDTH_A::_2X8BIT)
271    }
272}
273#[doc = "Field `seq_8plus2` reader - When select IF_DATA_WIDTH to be 8+2bit, odd/even pixel byte at CSI-D\\[11:4\\] will be rearranged to D\\[11:2\\]+2'b0 at the actual CSI data bus according to these sequences"]
274pub type SEQ_8PLUS2_R = crate::FieldReader<SEQ_8PLUS2_A>;
275#[doc = "When select IF_DATA_WIDTH to be 8+2bit, odd/even pixel byte at CSI-D\\[11:4\\] will be rearranged to D\\[11:2\\]+2'b0 at the actual CSI data bus according to these sequences\n\nValue on reset: 0"]
276#[derive(Clone, Copy, Debug, PartialEq, Eq)]
277#[repr(u8)]
278pub enum SEQ_8PLUS2_A {
279    #[doc = "0: 6'bx + D\\[9:8\\], D\\[7:0\\]"]
280    PD98_D70 = 0,
281    #[doc = "1: D\\[9:2\\], 6'bx + D\\[1:0\\]"]
282    D92_PD10 = 1,
283    #[doc = "2: D\\[7:0\\], D\\[9:8\\] + 6'bx"]
284    D70_D98P = 2,
285    #[doc = "3: D\\[7:0\\], 6'bx + D\\[9:8\\]"]
286    D70_PD98 = 3,
287}
288impl From<SEQ_8PLUS2_A> for u8 {
289    #[inline(always)]
290    fn from(variant: SEQ_8PLUS2_A) -> Self {
291        variant as _
292    }
293}
294impl crate::FieldSpec for SEQ_8PLUS2_A {
295    type Ux = u8;
296}
297impl SEQ_8PLUS2_R {
298    #[doc = "Get enumerated values variant"]
299    #[inline(always)]
300    pub const fn variant(&self) -> SEQ_8PLUS2_A {
301        match self.bits {
302            0 => SEQ_8PLUS2_A::PD98_D70,
303            1 => SEQ_8PLUS2_A::D92_PD10,
304            2 => SEQ_8PLUS2_A::D70_D98P,
305            3 => SEQ_8PLUS2_A::D70_PD98,
306            _ => unreachable!(),
307        }
308    }
309    #[doc = "6'bx + D\\[9:8\\], D\\[7:0\\]"]
310    #[inline(always)]
311    pub fn is_pd98_d70(&self) -> bool {
312        *self == SEQ_8PLUS2_A::PD98_D70
313    }
314    #[doc = "D\\[9:2\\], 6'bx + D\\[1:0\\]"]
315    #[inline(always)]
316    pub fn is_d92_pd10(&self) -> bool {
317        *self == SEQ_8PLUS2_A::D92_PD10
318    }
319    #[doc = "D\\[7:0\\], D\\[9:8\\] + 6'bx"]
320    #[inline(always)]
321    pub fn is_d70_d98p(&self) -> bool {
322        *self == SEQ_8PLUS2_A::D70_D98P
323    }
324    #[doc = "D\\[7:0\\], 6'bx + D\\[9:8\\]"]
325    #[inline(always)]
326    pub fn is_d70_pd98(&self) -> bool {
327        *self == SEQ_8PLUS2_A::D70_PD98
328    }
329}
330#[doc = "Field `seq_8plus2` writer - When select IF_DATA_WIDTH to be 8+2bit, odd/even pixel byte at CSI-D\\[11:4\\] will be rearranged to D\\[11:2\\]+2'b0 at the actual CSI data bus according to these sequences"]
331pub type SEQ_8PLUS2_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, SEQ_8PLUS2_A>;
332impl<'a, REG> SEQ_8PLUS2_W<'a, REG>
333where
334    REG: crate::Writable + crate::RegisterSpec,
335    REG::Ux: From<u8>,
336{
337    #[doc = "6'bx + D\\[9:8\\], D\\[7:0\\]"]
338    #[inline(always)]
339    pub fn pd98_d70(self) -> &'a mut crate::W<REG> {
340        self.variant(SEQ_8PLUS2_A::PD98_D70)
341    }
342    #[doc = "D\\[9:2\\], 6'bx + D\\[1:0\\]"]
343    #[inline(always)]
344    pub fn d92_pd10(self) -> &'a mut crate::W<REG> {
345        self.variant(SEQ_8PLUS2_A::D92_PD10)
346    }
347    #[doc = "D\\[7:0\\], D\\[9:8\\] + 6'bx"]
348    #[inline(always)]
349    pub fn d70_d98p(self) -> &'a mut crate::W<REG> {
350        self.variant(SEQ_8PLUS2_A::D70_D98P)
351    }
352    #[doc = "D\\[7:0\\], 6'bx + D\\[9:8\\]"]
353    #[inline(always)]
354    pub fn d70_pd98(self) -> &'a mut crate::W<REG> {
355        self.variant(SEQ_8PLUS2_A::D70_PD98)
356    }
357}
358#[doc = "Field `ddr_sample_mode_en` reader - "]
359pub type DDR_SAMPLE_MODE_EN_R = crate::BitReader<DDR_SAMPLE_MODE_EN_A>;
360#[doc = "\n\nValue on reset: 0"]
361#[derive(Clone, Copy, Debug, PartialEq, Eq)]
362pub enum DDR_SAMPLE_MODE_EN_A {
363    #[doc = "0: `0`"]
364    DISABLE = 0,
365    #[doc = "1: `1`"]
366    ENABLE = 1,
367}
368impl From<DDR_SAMPLE_MODE_EN_A> for bool {
369    #[inline(always)]
370    fn from(variant: DDR_SAMPLE_MODE_EN_A) -> Self {
371        variant as u8 != 0
372    }
373}
374impl DDR_SAMPLE_MODE_EN_R {
375    #[doc = "Get enumerated values variant"]
376    #[inline(always)]
377    pub const fn variant(&self) -> DDR_SAMPLE_MODE_EN_A {
378        match self.bits {
379            false => DDR_SAMPLE_MODE_EN_A::DISABLE,
380            true => DDR_SAMPLE_MODE_EN_A::ENABLE,
381        }
382    }
383    #[doc = "`0`"]
384    #[inline(always)]
385    pub fn is_disable(&self) -> bool {
386        *self == DDR_SAMPLE_MODE_EN_A::DISABLE
387    }
388    #[doc = "`1`"]
389    #[inline(always)]
390    pub fn is_enable(&self) -> bool {
391        *self == DDR_SAMPLE_MODE_EN_A::ENABLE
392    }
393}
394#[doc = "Field `ddr_sample_mode_en` writer - "]
395pub type DDR_SAMPLE_MODE_EN_W<'a, REG> = crate::BitWriter<'a, REG, DDR_SAMPLE_MODE_EN_A>;
396impl<'a, REG> DDR_SAMPLE_MODE_EN_W<'a, REG>
397where
398    REG: crate::Writable + crate::RegisterSpec,
399{
400    #[doc = "`0`"]
401    #[inline(always)]
402    pub fn disable(self) -> &'a mut crate::W<REG> {
403        self.variant(DDR_SAMPLE_MODE_EN_A::DISABLE)
404    }
405    #[doc = "`1`"]
406    #[inline(always)]
407    pub fn enable(self) -> &'a mut crate::W<REG> {
408        self.variant(DDR_SAMPLE_MODE_EN_A::ENABLE)
409    }
410}
411#[doc = "Field `field_dt_mode` reader - only valid when CSI_IF is YUB and source type is interlaced"]
412pub type FIELD_DT_MODE_R = crate::FieldReader<FIELD_DT_MODE_A>;
413#[doc = "only valid when CSI_IF is YUB and source type is interlaced\n\nValue on reset: 0"]
414#[derive(Clone, Copy, Debug, PartialEq, Eq)]
415#[repr(u8)]
416pub enum FIELD_DT_MODE_A {
417    #[doc = "0: by both field and vsync"]
418    BY_FIELD_VSYNC = 0,
419    #[doc = "1: by field"]
420    BY_FIELD = 1,
421    #[doc = "2: by vsync"]
422    BY_VSYNC = 2,
423}
424impl From<FIELD_DT_MODE_A> for u8 {
425    #[inline(always)]
426    fn from(variant: FIELD_DT_MODE_A) -> Self {
427        variant as _
428    }
429}
430impl crate::FieldSpec for FIELD_DT_MODE_A {
431    type Ux = u8;
432}
433impl FIELD_DT_MODE_R {
434    #[doc = "Get enumerated values variant"]
435    #[inline(always)]
436    pub const fn variant(&self) -> Option<FIELD_DT_MODE_A> {
437        match self.bits {
438            0 => Some(FIELD_DT_MODE_A::BY_FIELD_VSYNC),
439            1 => Some(FIELD_DT_MODE_A::BY_FIELD),
440            2 => Some(FIELD_DT_MODE_A::BY_VSYNC),
441            _ => None,
442        }
443    }
444    #[doc = "by both field and vsync"]
445    #[inline(always)]
446    pub fn is_by_field_vsync(&self) -> bool {
447        *self == FIELD_DT_MODE_A::BY_FIELD_VSYNC
448    }
449    #[doc = "by field"]
450    #[inline(always)]
451    pub fn is_by_field(&self) -> bool {
452        *self == FIELD_DT_MODE_A::BY_FIELD
453    }
454    #[doc = "by vsync"]
455    #[inline(always)]
456    pub fn is_by_vsync(&self) -> bool {
457        *self == FIELD_DT_MODE_A::BY_VSYNC
458    }
459}
460#[doc = "Field `field_dt_mode` writer - only valid when CSI_IF is YUB and source type is interlaced"]
461pub type FIELD_DT_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, FIELD_DT_MODE_A>;
462impl<'a, REG> FIELD_DT_MODE_W<'a, REG>
463where
464    REG: crate::Writable + crate::RegisterSpec,
465    REG::Ux: From<u8>,
466{
467    #[doc = "by both field and vsync"]
468    #[inline(always)]
469    pub fn by_field_vsync(self) -> &'a mut crate::W<REG> {
470        self.variant(FIELD_DT_MODE_A::BY_FIELD_VSYNC)
471    }
472    #[doc = "by field"]
473    #[inline(always)]
474    pub fn by_field(self) -> &'a mut crate::W<REG> {
475        self.variant(FIELD_DT_MODE_A::BY_FIELD)
476    }
477    #[doc = "by vsync"]
478    #[inline(always)]
479    pub fn by_vsync(self) -> &'a mut crate::W<REG> {
480        self.variant(FIELD_DT_MODE_A::BY_VSYNC)
481    }
482}
483#[doc = "Field `clk_pol` reader - Data clock type"]
484pub type CLK_POL_R = crate::BitReader<CLK_POL_A>;
485#[doc = "Data clock type\n\nValue on reset: 1"]
486#[derive(Clone, Copy, Debug, PartialEq, Eq)]
487pub enum CLK_POL_A {
488    #[doc = "0: active in rising edge"]
489    RISING = 0,
490    #[doc = "1: active in falling edge"]
491    FALLING = 1,
492}
493impl From<CLK_POL_A> for bool {
494    #[inline(always)]
495    fn from(variant: CLK_POL_A) -> Self {
496        variant as u8 != 0
497    }
498}
499impl CLK_POL_R {
500    #[doc = "Get enumerated values variant"]
501    #[inline(always)]
502    pub const fn variant(&self) -> CLK_POL_A {
503        match self.bits {
504            false => CLK_POL_A::RISING,
505            true => CLK_POL_A::FALLING,
506        }
507    }
508    #[doc = "active in rising edge"]
509    #[inline(always)]
510    pub fn is_rising(&self) -> bool {
511        *self == CLK_POL_A::RISING
512    }
513    #[doc = "active in falling edge"]
514    #[inline(always)]
515    pub fn is_falling(&self) -> bool {
516        *self == CLK_POL_A::FALLING
517    }
518}
519#[doc = "Field `clk_pol` writer - Data clock type"]
520pub type CLK_POL_W<'a, REG> = crate::BitWriter<'a, REG, CLK_POL_A>;
521impl<'a, REG> CLK_POL_W<'a, REG>
522where
523    REG: crate::Writable + crate::RegisterSpec,
524{
525    #[doc = "active in rising edge"]
526    #[inline(always)]
527    pub fn rising(self) -> &'a mut crate::W<REG> {
528        self.variant(CLK_POL_A::RISING)
529    }
530    #[doc = "active in falling edge"]
531    #[inline(always)]
532    pub fn falling(self) -> &'a mut crate::W<REG> {
533        self.variant(CLK_POL_A::FALLING)
534    }
535}
536#[doc = "Field `href_pol` reader - Href polarity\n\nThis register is not applied to CCIR656 interface"]
537pub type HREF_POL_R = crate::BitReader<HREF_POL_A>;
538#[doc = "Href polarity\n\nThis register is not applied to CCIR656 interface\n\nValue on reset: 0"]
539#[derive(Clone, Copy, Debug, PartialEq, Eq)]
540pub enum HREF_POL_A {
541    #[doc = "0: `0`"]
542    NEGATIVE = 0,
543    #[doc = "1: `1`"]
544    POSITIVE = 1,
545}
546impl From<HREF_POL_A> for bool {
547    #[inline(always)]
548    fn from(variant: HREF_POL_A) -> Self {
549        variant as u8 != 0
550    }
551}
552impl HREF_POL_R {
553    #[doc = "Get enumerated values variant"]
554    #[inline(always)]
555    pub const fn variant(&self) -> HREF_POL_A {
556        match self.bits {
557            false => HREF_POL_A::NEGATIVE,
558            true => HREF_POL_A::POSITIVE,
559        }
560    }
561    #[doc = "`0`"]
562    #[inline(always)]
563    pub fn is_negative(&self) -> bool {
564        *self == HREF_POL_A::NEGATIVE
565    }
566    #[doc = "`1`"]
567    #[inline(always)]
568    pub fn is_positive(&self) -> bool {
569        *self == HREF_POL_A::POSITIVE
570    }
571}
572#[doc = "Field `href_pol` writer - Href polarity\n\nThis register is not applied to CCIR656 interface"]
573pub type HREF_POL_W<'a, REG> = crate::BitWriter<'a, REG, HREF_POL_A>;
574impl<'a, REG> HREF_POL_W<'a, REG>
575where
576    REG: crate::Writable + crate::RegisterSpec,
577{
578    #[doc = "`0`"]
579    #[inline(always)]
580    pub fn negative(self) -> &'a mut crate::W<REG> {
581        self.variant(HREF_POL_A::NEGATIVE)
582    }
583    #[doc = "`1`"]
584    #[inline(always)]
585    pub fn positive(self) -> &'a mut crate::W<REG> {
586        self.variant(HREF_POL_A::POSITIVE)
587    }
588}
589#[doc = "Field `vref_pol` reader - Vref polarity\n\nThis register is not applied to CCIR656 interface"]
590pub type VREF_POL_R = crate::BitReader<VREF_POL_A>;
591#[doc = "Vref polarity\n\nThis register is not applied to CCIR656 interface\n\nValue on reset: 1"]
592#[derive(Clone, Copy, Debug, PartialEq, Eq)]
593pub enum VREF_POL_A {
594    #[doc = "0: `0`"]
595    NEGATIVE = 0,
596    #[doc = "1: `1`"]
597    POSITIVE = 1,
598}
599impl From<VREF_POL_A> for bool {
600    #[inline(always)]
601    fn from(variant: VREF_POL_A) -> Self {
602        variant as u8 != 0
603    }
604}
605impl VREF_POL_R {
606    #[doc = "Get enumerated values variant"]
607    #[inline(always)]
608    pub const fn variant(&self) -> VREF_POL_A {
609        match self.bits {
610            false => VREF_POL_A::NEGATIVE,
611            true => VREF_POL_A::POSITIVE,
612        }
613    }
614    #[doc = "`0`"]
615    #[inline(always)]
616    pub fn is_negative(&self) -> bool {
617        *self == VREF_POL_A::NEGATIVE
618    }
619    #[doc = "`1`"]
620    #[inline(always)]
621    pub fn is_positive(&self) -> bool {
622        *self == VREF_POL_A::POSITIVE
623    }
624}
625#[doc = "Field `vref_pol` writer - Vref polarity\n\nThis register is not applied to CCIR656 interface"]
626pub type VREF_POL_W<'a, REG> = crate::BitWriter<'a, REG, VREF_POL_A>;
627impl<'a, REG> VREF_POL_W<'a, REG>
628where
629    REG: crate::Writable + crate::RegisterSpec,
630{
631    #[doc = "`0`"]
632    #[inline(always)]
633    pub fn negative(self) -> &'a mut crate::W<REG> {
634        self.variant(VREF_POL_A::NEGATIVE)
635    }
636    #[doc = "`1`"]
637    #[inline(always)]
638    pub fn positive(self) -> &'a mut crate::W<REG> {
639        self.variant(VREF_POL_A::POSITIVE)
640    }
641}
642#[doc = "Field `field` reader - Field polarity (For YUV HV timing) / Field sequence (For BT656 timing)"]
643pub type FIELD_R = crate::BitReader<FIELD_A>;
644#[doc = "Field polarity (For YUV HV timing) / Field sequence (For BT656 timing)\n\nValue on reset: 0"]
645#[derive(Clone, Copy, Debug, PartialEq, Eq)]
646pub enum FIELD_A {
647    #[doc = "0: `0`"]
648    NEGATIVE_NORMAL_SEQ = 0,
649    #[doc = "1: `1`"]
650    POSITIVE_INVERSE_SEQ = 1,
651}
652impl From<FIELD_A> for bool {
653    #[inline(always)]
654    fn from(variant: FIELD_A) -> Self {
655        variant as u8 != 0
656    }
657}
658impl FIELD_R {
659    #[doc = "Get enumerated values variant"]
660    #[inline(always)]
661    pub const fn variant(&self) -> FIELD_A {
662        match self.bits {
663            false => FIELD_A::NEGATIVE_NORMAL_SEQ,
664            true => FIELD_A::POSITIVE_INVERSE_SEQ,
665        }
666    }
667    #[doc = "`0`"]
668    #[inline(always)]
669    pub fn is_negative_normal_seq(&self) -> bool {
670        *self == FIELD_A::NEGATIVE_NORMAL_SEQ
671    }
672    #[doc = "`1`"]
673    #[inline(always)]
674    pub fn is_positive_inverse_seq(&self) -> bool {
675        *self == FIELD_A::POSITIVE_INVERSE_SEQ
676    }
677}
678#[doc = "Field `field` writer - Field polarity (For YUV HV timing) / Field sequence (For BT656 timing)"]
679pub type FIELD_W<'a, REG> = crate::BitWriter<'a, REG, FIELD_A>;
680impl<'a, REG> FIELD_W<'a, REG>
681where
682    REG: crate::Writable + crate::RegisterSpec,
683{
684    #[doc = "`0`"]
685    #[inline(always)]
686    pub fn negative_normal_seq(self) -> &'a mut crate::W<REG> {
687        self.variant(FIELD_A::NEGATIVE_NORMAL_SEQ)
688    }
689    #[doc = "`1`"]
690    #[inline(always)]
691    pub fn positive_inverse_seq(self) -> &'a mut crate::W<REG> {
692        self.variant(FIELD_A::POSITIVE_INVERSE_SEQ)
693    }
694}
695#[doc = "Field `source_type` reader - Bit 20-23 corresponding to the SRC_TYPEs for channel 0-3"]
696pub type SOURCE_TYPE_R = crate::FieldReader<SOURCE_TYPE_A>;
697#[doc = "Bit 20-23 corresponding to the SRC_TYPEs for channel 0-3\n\nValue on reset: 0"]
698#[derive(Clone, Copy, Debug, PartialEq, Eq)]
699#[repr(u8)]
700pub enum SOURCE_TYPE_A {
701    #[doc = "0: `0`"]
702    P_ROGRESSED = 0,
703    #[doc = "1: `1`"]
704    INTERLACED = 1,
705}
706impl From<SOURCE_TYPE_A> for u8 {
707    #[inline(always)]
708    fn from(variant: SOURCE_TYPE_A) -> Self {
709        variant as _
710    }
711}
712impl crate::FieldSpec for SOURCE_TYPE_A {
713    type Ux = u8;
714}
715impl SOURCE_TYPE_R {
716    #[doc = "Get enumerated values variant"]
717    #[inline(always)]
718    pub const fn variant(&self) -> Option<SOURCE_TYPE_A> {
719        match self.bits {
720            0 => Some(SOURCE_TYPE_A::P_ROGRESSED),
721            1 => Some(SOURCE_TYPE_A::INTERLACED),
722            _ => None,
723        }
724    }
725    #[doc = "`0`"]
726    #[inline(always)]
727    pub fn is_p_rogressed(&self) -> bool {
728        *self == SOURCE_TYPE_A::P_ROGRESSED
729    }
730    #[doc = "`1`"]
731    #[inline(always)]
732    pub fn is_interlaced(&self) -> bool {
733        *self == SOURCE_TYPE_A::INTERLACED
734    }
735}
736#[doc = "Field `source_type` writer - Bit 20-23 corresponding to the SRC_TYPEs for channel 0-3"]
737pub type SOURCE_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 4, SOURCE_TYPE_A>;
738impl<'a, REG> SOURCE_TYPE_W<'a, REG>
739where
740    REG: crate::Writable + crate::RegisterSpec,
741    REG::Ux: From<u8>,
742{
743    #[doc = "`0`"]
744    #[inline(always)]
745    pub fn p_rogressed(self) -> &'a mut crate::W<REG> {
746        self.variant(SOURCE_TYPE_A::P_ROGRESSED)
747    }
748    #[doc = "`1`"]
749    #[inline(always)]
750    pub fn interlaced(self) -> &'a mut crate::W<REG> {
751        self.variant(SOURCE_TYPE_A::INTERLACED)
752    }
753}
754#[doc = "Field `field_dt_pclk_shift` reader - Only for vsync detected field mode, the odd field permitted pclk\n\nshift = 4 * FIELD_DT_PCLK_SHIFT"]
755pub type FIELD_DT_PCLK_SHIFT_R = crate::FieldReader;
756#[doc = "Field `field_dt_pclk_shift` writer - Only for vsync detected field mode, the odd field permitted pclk\n\nshift = 4 * FIELD_DT_PCLK_SHIFT"]
757pub type FIELD_DT_PCLK_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
758#[doc = "Field `yuv420_line_order` reader - "]
759pub type YUV420_LINE_ORDER_R = crate::BitReader<YUV420_LINE_ORDER_A>;
760#[doc = "\n\nValue on reset: 0"]
761#[derive(Clone, Copy, Debug, PartialEq, Eq)]
762pub enum YUV420_LINE_ORDER_A {
763    #[doc = "0: YUV420 input in Y_YC_Y_YC line order"]
764    Y_YC_Y_YC = 0,
765    #[doc = "1: YUV420 input in YC_Y_YC_Y line order"]
766    YC_Y_YC_Y = 1,
767}
768impl From<YUV420_LINE_ORDER_A> for bool {
769    #[inline(always)]
770    fn from(variant: YUV420_LINE_ORDER_A) -> Self {
771        variant as u8 != 0
772    }
773}
774impl YUV420_LINE_ORDER_R {
775    #[doc = "Get enumerated values variant"]
776    #[inline(always)]
777    pub const fn variant(&self) -> YUV420_LINE_ORDER_A {
778        match self.bits {
779            false => YUV420_LINE_ORDER_A::Y_YC_Y_YC,
780            true => YUV420_LINE_ORDER_A::YC_Y_YC_Y,
781        }
782    }
783    #[doc = "YUV420 input in Y_YC_Y_YC line order"]
784    #[inline(always)]
785    pub fn is_y_yc_y_yc(&self) -> bool {
786        *self == YUV420_LINE_ORDER_A::Y_YC_Y_YC
787    }
788    #[doc = "YUV420 input in YC_Y_YC_Y line order"]
789    #[inline(always)]
790    pub fn is_yc_y_yc_y(&self) -> bool {
791        *self == YUV420_LINE_ORDER_A::YC_Y_YC_Y
792    }
793}
794#[doc = "Field `yuv420_line_order` writer - "]
795pub type YUV420_LINE_ORDER_W<'a, REG> = crate::BitWriter<'a, REG, YUV420_LINE_ORDER_A>;
796impl<'a, REG> YUV420_LINE_ORDER_W<'a, REG>
797where
798    REG: crate::Writable + crate::RegisterSpec,
799{
800    #[doc = "YUV420 input in Y_YC_Y_YC line order"]
801    #[inline(always)]
802    pub fn y_yc_y_yc(self) -> &'a mut crate::W<REG> {
803        self.variant(YUV420_LINE_ORDER_A::Y_YC_Y_YC)
804    }
805    #[doc = "YUV420 input in YC_Y_YC_Y line order"]
806    #[inline(always)]
807    pub fn yc_y_yc_y(self) -> &'a mut crate::W<REG> {
808        self.variant(YUV420_LINE_ORDER_A::YC_Y_YC_Y)
809    }
810}
811impl R {
812    #[doc = "Bits 0:4"]
813    #[inline(always)]
814    pub fn csi_if(&self) -> CSI_IF_R {
815        CSI_IF_R::new((self.bits & 0x1f) as u8)
816    }
817    #[doc = "Bits 6:7 - Input data sequence, only valid for YUV422 and YUV420 input format"]
818    #[inline(always)]
819    pub fn input_seq(&self) -> INPUT_SEQ_R {
820        INPUT_SEQ_R::new(((self.bits >> 6) & 3) as u8)
821    }
822    #[doc = "Bits 8:10"]
823    #[inline(always)]
824    pub fn if_data_width(&self) -> IF_DATA_WIDTH_R {
825        IF_DATA_WIDTH_R::new(((self.bits >> 8) & 7) as u8)
826    }
827    #[doc = "Bits 11:12 - When select IF_DATA_WIDTH to be 8+2bit, odd/even pixel byte at CSI-D\\[11:4\\] will be rearranged to D\\[11:2\\]+2'b0 at the actual CSI data bus according to these sequences"]
828    #[inline(always)]
829    pub fn seq_8plus2(&self) -> SEQ_8PLUS2_R {
830        SEQ_8PLUS2_R::new(((self.bits >> 11) & 3) as u8)
831    }
832    #[doc = "Bit 13"]
833    #[inline(always)]
834    pub fn ddr_sample_mode_en(&self) -> DDR_SAMPLE_MODE_EN_R {
835        DDR_SAMPLE_MODE_EN_R::new(((self.bits >> 13) & 1) != 0)
836    }
837    #[doc = "Bits 14:15 - only valid when CSI_IF is YUB and source type is interlaced"]
838    #[inline(always)]
839    pub fn field_dt_mode(&self) -> FIELD_DT_MODE_R {
840        FIELD_DT_MODE_R::new(((self.bits >> 14) & 3) as u8)
841    }
842    #[doc = "Bit 16 - Data clock type"]
843    #[inline(always)]
844    pub fn clk_pol(&self) -> CLK_POL_R {
845        CLK_POL_R::new(((self.bits >> 16) & 1) != 0)
846    }
847    #[doc = "Bit 17 - Href polarity\n\nThis register is not applied to CCIR656 interface"]
848    #[inline(always)]
849    pub fn href_pol(&self) -> HREF_POL_R {
850        HREF_POL_R::new(((self.bits >> 17) & 1) != 0)
851    }
852    #[doc = "Bit 18 - Vref polarity\n\nThis register is not applied to CCIR656 interface"]
853    #[inline(always)]
854    pub fn vref_pol(&self) -> VREF_POL_R {
855        VREF_POL_R::new(((self.bits >> 18) & 1) != 0)
856    }
857    #[doc = "Bit 19 - Field polarity (For YUV HV timing) / Field sequence (For BT656 timing)"]
858    #[inline(always)]
859    pub fn field(&self) -> FIELD_R {
860        FIELD_R::new(((self.bits >> 19) & 1) != 0)
861    }
862    #[doc = "Bits 20:23 - Bit 20-23 corresponding to the SRC_TYPEs for channel 0-3"]
863    #[inline(always)]
864    pub fn source_type(&self) -> SOURCE_TYPE_R {
865        SOURCE_TYPE_R::new(((self.bits >> 20) & 0x0f) as u8)
866    }
867    #[doc = "Bits 24:27 - Only for vsync detected field mode, the odd field permitted pclk\n\nshift = 4 * FIELD_DT_PCLK_SHIFT"]
868    #[inline(always)]
869    pub fn field_dt_pclk_shift(&self) -> FIELD_DT_PCLK_SHIFT_R {
870        FIELD_DT_PCLK_SHIFT_R::new(((self.bits >> 24) & 0x0f) as u8)
871    }
872    #[doc = "Bit 31"]
873    #[inline(always)]
874    pub fn yuv420_line_order(&self) -> YUV420_LINE_ORDER_R {
875        YUV420_LINE_ORDER_R::new(((self.bits >> 31) & 1) != 0)
876    }
877}
878impl W {
879    #[doc = "Bits 0:4"]
880    #[inline(always)]
881    #[must_use]
882    pub fn csi_if(&mut self) -> CSI_IF_W<PRS_NCSIC_IF_CFG_SPEC> {
883        CSI_IF_W::new(self, 0)
884    }
885    #[doc = "Bits 6:7 - Input data sequence, only valid for YUV422 and YUV420 input format"]
886    #[inline(always)]
887    #[must_use]
888    pub fn input_seq(&mut self) -> INPUT_SEQ_W<PRS_NCSIC_IF_CFG_SPEC> {
889        INPUT_SEQ_W::new(self, 6)
890    }
891    #[doc = "Bits 8:10"]
892    #[inline(always)]
893    #[must_use]
894    pub fn if_data_width(&mut self) -> IF_DATA_WIDTH_W<PRS_NCSIC_IF_CFG_SPEC> {
895        IF_DATA_WIDTH_W::new(self, 8)
896    }
897    #[doc = "Bits 11:12 - When select IF_DATA_WIDTH to be 8+2bit, odd/even pixel byte at CSI-D\\[11:4\\] will be rearranged to D\\[11:2\\]+2'b0 at the actual CSI data bus according to these sequences"]
898    #[inline(always)]
899    #[must_use]
900    pub fn seq_8plus2(&mut self) -> SEQ_8PLUS2_W<PRS_NCSIC_IF_CFG_SPEC> {
901        SEQ_8PLUS2_W::new(self, 11)
902    }
903    #[doc = "Bit 13"]
904    #[inline(always)]
905    #[must_use]
906    pub fn ddr_sample_mode_en(&mut self) -> DDR_SAMPLE_MODE_EN_W<PRS_NCSIC_IF_CFG_SPEC> {
907        DDR_SAMPLE_MODE_EN_W::new(self, 13)
908    }
909    #[doc = "Bits 14:15 - only valid when CSI_IF is YUB and source type is interlaced"]
910    #[inline(always)]
911    #[must_use]
912    pub fn field_dt_mode(&mut self) -> FIELD_DT_MODE_W<PRS_NCSIC_IF_CFG_SPEC> {
913        FIELD_DT_MODE_W::new(self, 14)
914    }
915    #[doc = "Bit 16 - Data clock type"]
916    #[inline(always)]
917    #[must_use]
918    pub fn clk_pol(&mut self) -> CLK_POL_W<PRS_NCSIC_IF_CFG_SPEC> {
919        CLK_POL_W::new(self, 16)
920    }
921    #[doc = "Bit 17 - Href polarity\n\nThis register is not applied to CCIR656 interface"]
922    #[inline(always)]
923    #[must_use]
924    pub fn href_pol(&mut self) -> HREF_POL_W<PRS_NCSIC_IF_CFG_SPEC> {
925        HREF_POL_W::new(self, 17)
926    }
927    #[doc = "Bit 18 - Vref polarity\n\nThis register is not applied to CCIR656 interface"]
928    #[inline(always)]
929    #[must_use]
930    pub fn vref_pol(&mut self) -> VREF_POL_W<PRS_NCSIC_IF_CFG_SPEC> {
931        VREF_POL_W::new(self, 18)
932    }
933    #[doc = "Bit 19 - Field polarity (For YUV HV timing) / Field sequence (For BT656 timing)"]
934    #[inline(always)]
935    #[must_use]
936    pub fn field(&mut self) -> FIELD_W<PRS_NCSIC_IF_CFG_SPEC> {
937        FIELD_W::new(self, 19)
938    }
939    #[doc = "Bits 20:23 - Bit 20-23 corresponding to the SRC_TYPEs for channel 0-3"]
940    #[inline(always)]
941    #[must_use]
942    pub fn source_type(&mut self) -> SOURCE_TYPE_W<PRS_NCSIC_IF_CFG_SPEC> {
943        SOURCE_TYPE_W::new(self, 20)
944    }
945    #[doc = "Bits 24:27 - Only for vsync detected field mode, the odd field permitted pclk\n\nshift = 4 * FIELD_DT_PCLK_SHIFT"]
946    #[inline(always)]
947    #[must_use]
948    pub fn field_dt_pclk_shift(&mut self) -> FIELD_DT_PCLK_SHIFT_W<PRS_NCSIC_IF_CFG_SPEC> {
949        FIELD_DT_PCLK_SHIFT_W::new(self, 24)
950    }
951    #[doc = "Bit 31"]
952    #[inline(always)]
953    #[must_use]
954    pub fn yuv420_line_order(&mut self) -> YUV420_LINE_ORDER_W<PRS_NCSIC_IF_CFG_SPEC> {
955        YUV420_LINE_ORDER_W::new(self, 31)
956    }
957    #[doc = r" Writes raw bits to the register."]
958    #[doc = r""]
959    #[doc = r" # Safety"]
960    #[doc = r""]
961    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
962    #[inline(always)]
963    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
964        self.bits = bits;
965        self
966    }
967}
968#[doc = "Parser NCSIC Interface Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prs_ncsic_if_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`prs_ncsic_if_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
969pub struct PRS_NCSIC_IF_CFG_SPEC;
970impl crate::RegisterSpec for PRS_NCSIC_IF_CFG_SPEC {
971    type Ux = u32;
972}
973#[doc = "`read()` method returns [`prs_ncsic_if_cfg::R`](R) reader structure"]
974impl crate::Readable for PRS_NCSIC_IF_CFG_SPEC {}
975#[doc = "`write(|w| ..)` method takes [`prs_ncsic_if_cfg::W`](W) writer structure"]
976impl crate::Writable for PRS_NCSIC_IF_CFG_SPEC {
977    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
978    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
979}
980#[doc = "`reset()` method sets prs_ncsic_if_cfg to value 0x0105_0080"]
981impl crate::Resettable for PRS_NCSIC_IF_CFG_SPEC {
982    const RESET_VALUE: Self::Ux = 0x0105_0080;
983}
d1_pac/csic/csic_parser0/prs_ncsic_if_cfg.rs

d1_pac/csic/csic_parser0/
prs_ncsic_if_cfg.rs
