d1_pac/csic/csic_parser0/
prs_ch_input_para0.rs

1#[doc = "Register `prs_ch%s_input_para0` reader"]
2pub type R = crate::R<PRS_CH_INPUT_PARA0_SPEC>;
3#[doc = "Field `input_src_type` reader - "]
4pub type INPUT_SRC_TYPE_R = crate::BitReader<INPUT_SRC_TYPE_A>;
5#[doc = "\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum INPUT_SRC_TYPE_A {
8    #[doc = "0: `0`"]
9    PROGRESS = 0,
10    #[doc = "1: `1`"]
11    INTERLACE = 1,
12}
13impl From<INPUT_SRC_TYPE_A> for bool {
14    #[inline(always)]
15    fn from(variant: INPUT_SRC_TYPE_A) -> Self {
16        variant as u8 != 0
17    }
18}
19impl INPUT_SRC_TYPE_R {
20    #[doc = "Get enumerated values variant"]
21    #[inline(always)]
22    pub const fn variant(&self) -> INPUT_SRC_TYPE_A {
23        match self.bits {
24            false => INPUT_SRC_TYPE_A::PROGRESS,
25            true => INPUT_SRC_TYPE_A::INTERLACE,
26        }
27    }
28    #[doc = "`0`"]
29    #[inline(always)]
30    pub fn is_progress(&self) -> bool {
31        *self == INPUT_SRC_TYPE_A::PROGRESS
32    }
33    #[doc = "`1`"]
34    #[inline(always)]
35    pub fn is_interlace(&self) -> bool {
36        *self == INPUT_SRC_TYPE_A::INTERLACE
37    }
38}
39impl R {
40    #[doc = "Bit 0"]
41    #[inline(always)]
42    pub fn input_src_type(&self) -> INPUT_SRC_TYPE_R {
43        INPUT_SRC_TYPE_R::new((self.bits & 1) != 0)
44    }
45}
46#[doc = "Parser Channel\\[i\\] Input Parameter0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`prs_ch_input_para0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct PRS_CH_INPUT_PARA0_SPEC;
48impl crate::RegisterSpec for PRS_CH_INPUT_PARA0_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`prs_ch_input_para0::R`](R) reader structure"]
52impl crate::Readable for PRS_CH_INPUT_PARA0_SPEC {}
53#[doc = "`reset()` method sets prs_ch%s_input_para0 to value 0"]
54impl crate::Resettable for PRS_CH_INPUT_PARA0_SPEC {
55    const RESET_VALUE: Self::Ux = 0;
56}
d1_pac/csic/csic_parser0/prs_ch_input_para0.rs

d1_pac/csic/csic_parser0/
prs_ch_input_para0.rs
