d1_pac/csic/csic_dma/
csic_dma_vi_to_th0.rs

1#[doc = "Register `csic_dma_vi_to_th0` reader"]
2pub type R = crate::R<CSIC_DMA_VI_TO_TH0_SPEC>;
3#[doc = "Register `csic_dma_vi_to_th0` writer"]
4pub type W = crate::W<CSIC_DMA_VI_TO_TH0_SPEC>;
5#[doc = "Field `vi_to_th0` reader - Video Input Timeout Threshold0\n\nSet VIDEO_INPUT_TO_INT_PD when VI Counter reaches TH0 after VI_TO_CNT_EN is set, the Time Unit is a 12M clock period."]
6pub type VI_TO_TH0_R = crate::FieldReader<u32>;
7#[doc = "Field `vi_to_th0` writer - Video Input Timeout Threshold0\n\nSet VIDEO_INPUT_TO_INT_PD when VI Counter reaches TH0 after VI_TO_CNT_EN is set, the Time Unit is a 12M clock period."]
8pub type VI_TO_TH0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31 - Video Input Timeout Threshold0\n\nSet VIDEO_INPUT_TO_INT_PD when VI Counter reaches TH0 after VI_TO_CNT_EN is set, the Time Unit is a 12M clock period."]
11    #[inline(always)]
12    pub fn vi_to_th0(&self) -> VI_TO_TH0_R {
13        VI_TO_TH0_R::new(self.bits)
14    }
15}
16impl W {
17    #[doc = "Bits 0:31 - Video Input Timeout Threshold0\n\nSet VIDEO_INPUT_TO_INT_PD when VI Counter reaches TH0 after VI_TO_CNT_EN is set, the Time Unit is a 12M clock period."]
18    #[inline(always)]
19    #[must_use]
20    pub fn vi_to_th0(&mut self) -> VI_TO_TH0_W<CSIC_DMA_VI_TO_TH0_SPEC> {
21        VI_TO_TH0_W::new(self, 0)
22    }
23    #[doc = r" Writes raw bits to the register."]
24    #[doc = r""]
25    #[doc = r" # Safety"]
26    #[doc = r""]
27    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
28    #[inline(always)]
29    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
30        self.bits = bits;
31        self
32    }
33}
34#[doc = "CSIC DMA Video Input Timeout Threshold0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csic_dma_vi_to_th0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csic_dma_vi_to_th0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
35pub struct CSIC_DMA_VI_TO_TH0_SPEC;
36impl crate::RegisterSpec for CSIC_DMA_VI_TO_TH0_SPEC {
37    type Ux = u32;
38}
39#[doc = "`read()` method returns [`csic_dma_vi_to_th0::R`](R) reader structure"]
40impl crate::Readable for CSIC_DMA_VI_TO_TH0_SPEC {}
41#[doc = "`write(|w| ..)` method takes [`csic_dma_vi_to_th0::W`](W) writer structure"]
42impl crate::Writable for CSIC_DMA_VI_TO_TH0_SPEC {
43    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
44    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
45}
46#[doc = "`reset()` method sets csic_dma_vi_to_th0 to value 0"]
47impl crate::Resettable for CSIC_DMA_VI_TO_TH0_SPEC {
48    const RESET_VALUE: Self::Ux = 0;
49}
d1_pac/csic/csic_dma/csic_dma_vi_to_th0.rs

d1_pac/csic/csic_dma/
csic_dma_vi_to_th0.rs
