d1_pac/csic/csic_dma/
csic_dma_pclk_stat.rs

1#[doc = "Register `csic_dma_pclk_stat` reader"]
2pub type R = crate::R<CSIC_DMA_PCLK_STAT_SPEC>;
3#[doc = "Register `csic_dma_pclk_stat` writer"]
4pub type W = crate::W<CSIC_DMA_PCLK_STAT_SPEC>;
5#[doc = "Field `pclk_cnt_line_min` reader - Indicates minimum pixel clock counter value for each line. Update at every vsync or framedone."]
6pub type PCLK_CNT_LINE_MIN_R = crate::FieldReader<u16>;
7#[doc = "Field `pclk_cnt_line_max` reader - Indicates maximum pixel clock counter value for each line. Update at every vsync or framedone."]
8pub type PCLK_CNT_LINE_MAX_R = crate::FieldReader<u16>;
9impl R {
10    #[doc = "Bits 0:14 - Indicates minimum pixel clock counter value for each line. Update at every vsync or framedone."]
11    #[inline(always)]
12    pub fn pclk_cnt_line_min(&self) -> PCLK_CNT_LINE_MIN_R {
13        PCLK_CNT_LINE_MIN_R::new((self.bits & 0x7fff) as u16)
14    }
15    #[doc = "Bits 16:30 - Indicates maximum pixel clock counter value for each line. Update at every vsync or framedone."]
16    #[inline(always)]
17    pub fn pclk_cnt_line_max(&self) -> PCLK_CNT_LINE_MAX_R {
18        PCLK_CNT_LINE_MAX_R::new(((self.bits >> 16) & 0x7fff) as u16)
19    }
20}
21impl W {
22    #[doc = r" Writes raw bits to the register."]
23    #[doc = r""]
24    #[doc = r" # Safety"]
25    #[doc = r""]
26    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
27    #[inline(always)]
28    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
29        self.bits = bits;
30        self
31    }
32}
33#[doc = "CSIC DMA PCLK Statistic Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csic_dma_pclk_stat::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csic_dma_pclk_stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
34pub struct CSIC_DMA_PCLK_STAT_SPEC;
35impl crate::RegisterSpec for CSIC_DMA_PCLK_STAT_SPEC {
36    type Ux = u32;
37}
38#[doc = "`read()` method returns [`csic_dma_pclk_stat::R`](R) reader structure"]
39impl crate::Readable for CSIC_DMA_PCLK_STAT_SPEC {}
40#[doc = "`write(|w| ..)` method takes [`csic_dma_pclk_stat::W`](W) writer structure"]
41impl crate::Writable for CSIC_DMA_PCLK_STAT_SPEC {
42    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
43    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
44}
45#[doc = "`reset()` method sets csic_dma_pclk_stat to value 0x7fff"]
46impl crate::Resettable for CSIC_DMA_PCLK_STAT_SPEC {
47    const RESET_VALUE: Self::Ux = 0x7fff;
48}
d1_pac/csic/csic_dma/csic_dma_pclk_stat.rs

d1_pac/csic/csic_dma/
csic_dma_pclk_stat.rs
