d1_pac/csic/csic_dma/
csic_dma_int_en.rs1#[doc = "Register `csic_dma_int_en` reader"]
2pub type R = crate::R<CSIC_DMA_INT_EN_SPEC>;
3#[doc = "Register `csic_dma_int_en` writer"]
4pub type W = crate::W<CSIC_DMA_INT_EN_SPEC>;
5#[doc = "Field `cd_int_en` reader - Capture done\n\nIndicates the CSI has completed capturing the image data. For still capture, the bit is set when one frame data has been written to buffer. For video capture, the bit is set when the last frame has been written to buffer after video capture has been disabled. For CCIR656 interface, if the output format is frame planar YCbCr 420 mode, the frame end means the field2 end, the other frame end means field end."]
6pub type CD_INT_EN_R = crate::BitReader;
7#[doc = "Field `cd_int_en` writer - Capture done\n\nIndicates the CSI has completed capturing the image data. For still capture, the bit is set when one frame data has been written to buffer. For video capture, the bit is set when the last frame has been written to buffer after video capture has been disabled. For CCIR656 interface, if the output format is frame planar YCbCr 420 mode, the frame end means the field2 end, the other frame end means field end."]
8pub type CD_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `fd_int_en` reader - Frame done\n\nIndicates the CSI has finished capturing an image frame. Applies to video capture mode. The bit is set after each completed frame capturing data is written to buffer as long as video capture remains enabled."]
10pub type FD_INT_EN_R = crate::BitReader;
11#[doc = "Field `fd_int_en` writer - Frame done\n\nIndicates the CSI has finished capturing an image frame. Applies to video capture mode. The bit is set after each completed frame capturing data is written to buffer as long as video capture remains enabled."]
12pub type FD_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `fifo0_of_int_en` reader - FIFO 0 overflow\n\nThe bit is set when the FIFO 0 became overflow."]
14pub type FIFO0_OF_INT_EN_R = crate::BitReader;
15#[doc = "Field `fifo0_of_int_en` writer - FIFO 0 overflow\n\nThe bit is set when the FIFO 0 became overflow."]
16pub type FIFO0_OF_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `fifo1_of_int_en` reader - FIFO 1 overflow\n\nThe bit is set when the FIFO 1 became overflow."]
18pub type FIFO1_OF_INT_EN_R = crate::BitReader;
19#[doc = "Field `fifo1_of_int_en` writer - FIFO 1 overflow\n\nThe bit is set when the FIFO 1 became overflow."]
20pub type FIFO1_OF_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `fifo2_of_int_en` reader - FIFO 2 overflow\n\nThe bit is set when the FIFO 2 became overflow."]
22pub type FIFO2_OF_INT_EN_R = crate::BitReader;
23#[doc = "Field `fifo2_of_int_en` writer - FIFO 2 overflow\n\nThe bit is set when the FIFO 2 became overflow."]
24pub type FIFO2_OF_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `lc_int_en` reader - Line counter flag The bit is set when the specific line has been written to dram every frame. The line number is set in the line counter register."]
26pub type LC_INT_EN_R = crate::BitReader;
27#[doc = "Field `lc_int_en` writer - Line counter flag The bit is set when the specific line has been written to dram every frame. The line number is set in the line counter register."]
28pub type LC_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `hb_of_int_en` reader - Hblank FIFO overflow The bit is set when 3 FIFOs still overflow after the hblank."]
30pub type HB_OF_INT_EN_R = crate::BitReader;
31#[doc = "Field `hb_of_int_en` writer - Hblank FIFO overflow The bit is set when 3 FIFOs still overflow after the hblank."]
32pub type HB_OF_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `vs_int_en` reader - vsync flag\n\nThe bit is set when vsync come. And at this time load the buffer address for the coming frame. So after this irq come, changing the buffer address could only effect next frame"]
34pub type VS_INT_EN_R = crate::BitReader;
35#[doc = "Field `vs_int_en` writer - vsync flag\n\nThe bit is set when vsync come. And at this time load the buffer address for the coming frame. So after this irq come, changing the buffer address could only effect next frame"]
36pub type VS_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `clr_frame_cnt_int_en` reader - Set a INT when clear Frame cnt."]
38pub type CLR_FRAME_CNT_INT_EN_R = crate::BitReader;
39#[doc = "Field `clr_frame_cnt_int_en` writer - Set a INT when clear Frame cnt."]
40pub type CLR_FRAME_CNT_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `video_input_to_int_en` reader - Set an INT when no video input exceeds the setting threshold time"]
42pub type VIDEO_INPUT_TO_INT_EN_R = crate::BitReader;
43#[doc = "Field `video_input_to_int_en` writer - Set an INT when no video input exceeds the setting threshold time"]
44pub type VIDEO_INPUT_TO_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `buf_addr_fifo_int_en` reader - Set an INT when content in BUF Address FIFO less than CSIC_DMA_BUFA_FIFO_THRESHOLD, only use in BUF Address FIFO MODE."]
46pub type BUF_ADDR_FIFO_INT_EN_R = crate::BitReader;
47#[doc = "Field `buf_addr_fifo_int_en` writer - Set an INT when content in BUF Address FIFO less than CSIC_DMA_BUFA_FIFO_THRESHOLD, only use in BUF Address FIFO MODE."]
48pub type BUF_ADDR_FIFO_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `stored_frm_cnt_int_en` reader - Set an INT when the value of CSIC_DMA_STORED_FRM_CNT reaches CSIC_DMA_STORED_FRM_THRESHOLD, only use in BUF Address FIFO MODE."]
50pub type STORED_FRM_CNT_INT_EN_R = crate::BitReader;
51#[doc = "Field `stored_frm_cnt_int_en` writer - Set an INT when the value of CSIC_DMA_STORED_FRM_CNT reaches CSIC_DMA_STORED_FRM_THRESHOLD, only use in BUF Address FIFO MODE."]
52pub type STORED_FRM_CNT_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `frm_lost_int_en` reader - Set an INT when frame starts with empty Buffer Address FIFO, only use in BUF Address FIFO MODE."]
54pub type FRM_LOST_INT_EN_R = crate::BitReader;
55#[doc = "Field `frm_lost_int_en` writer - Set an INT when frame starts with empty Buffer Address FIFO, only use in BUF Address FIFO MODE."]
56pub type FRM_LOST_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
57impl R {
58 #[doc = "Bit 0 - Capture done\n\nIndicates the CSI has completed capturing the image data. For still capture, the bit is set when one frame data has been written to buffer. For video capture, the bit is set when the last frame has been written to buffer after video capture has been disabled. For CCIR656 interface, if the output format is frame planar YCbCr 420 mode, the frame end means the field2 end, the other frame end means field end."]
59 #[inline(always)]
60 pub fn cd_int_en(&self) -> CD_INT_EN_R {
61 CD_INT_EN_R::new((self.bits & 1) != 0)
62 }
63 #[doc = "Bit 1 - Frame done\n\nIndicates the CSI has finished capturing an image frame. Applies to video capture mode. The bit is set after each completed frame capturing data is written to buffer as long as video capture remains enabled."]
64 #[inline(always)]
65 pub fn fd_int_en(&self) -> FD_INT_EN_R {
66 FD_INT_EN_R::new(((self.bits >> 1) & 1) != 0)
67 }
68 #[doc = "Bit 2 - FIFO 0 overflow\n\nThe bit is set when the FIFO 0 became overflow."]
69 #[inline(always)]
70 pub fn fifo0_of_int_en(&self) -> FIFO0_OF_INT_EN_R {
71 FIFO0_OF_INT_EN_R::new(((self.bits >> 2) & 1) != 0)
72 }
73 #[doc = "Bit 3 - FIFO 1 overflow\n\nThe bit is set when the FIFO 1 became overflow."]
74 #[inline(always)]
75 pub fn fifo1_of_int_en(&self) -> FIFO1_OF_INT_EN_R {
76 FIFO1_OF_INT_EN_R::new(((self.bits >> 3) & 1) != 0)
77 }
78 #[doc = "Bit 4 - FIFO 2 overflow\n\nThe bit is set when the FIFO 2 became overflow."]
79 #[inline(always)]
80 pub fn fifo2_of_int_en(&self) -> FIFO2_OF_INT_EN_R {
81 FIFO2_OF_INT_EN_R::new(((self.bits >> 4) & 1) != 0)
82 }
83 #[doc = "Bit 5 - Line counter flag The bit is set when the specific line has been written to dram every frame. The line number is set in the line counter register."]
84 #[inline(always)]
85 pub fn lc_int_en(&self) -> LC_INT_EN_R {
86 LC_INT_EN_R::new(((self.bits >> 5) & 1) != 0)
87 }
88 #[doc = "Bit 6 - Hblank FIFO overflow The bit is set when 3 FIFOs still overflow after the hblank."]
89 #[inline(always)]
90 pub fn hb_of_int_en(&self) -> HB_OF_INT_EN_R {
91 HB_OF_INT_EN_R::new(((self.bits >> 6) & 1) != 0)
92 }
93 #[doc = "Bit 7 - vsync flag\n\nThe bit is set when vsync come. And at this time load the buffer address for the coming frame. So after this irq come, changing the buffer address could only effect next frame"]
94 #[inline(always)]
95 pub fn vs_int_en(&self) -> VS_INT_EN_R {
96 VS_INT_EN_R::new(((self.bits >> 7) & 1) != 0)
97 }
98 #[doc = "Bit 11 - Set a INT when clear Frame cnt."]
99 #[inline(always)]
100 pub fn clr_frame_cnt_int_en(&self) -> CLR_FRAME_CNT_INT_EN_R {
101 CLR_FRAME_CNT_INT_EN_R::new(((self.bits >> 11) & 1) != 0)
102 }
103 #[doc = "Bit 12 - Set an INT when no video input exceeds the setting threshold time"]
104 #[inline(always)]
105 pub fn video_input_to_int_en(&self) -> VIDEO_INPUT_TO_INT_EN_R {
106 VIDEO_INPUT_TO_INT_EN_R::new(((self.bits >> 12) & 1) != 0)
107 }
108 #[doc = "Bit 13 - Set an INT when content in BUF Address FIFO less than CSIC_DMA_BUFA_FIFO_THRESHOLD, only use in BUF Address FIFO MODE."]
109 #[inline(always)]
110 pub fn buf_addr_fifo_int_en(&self) -> BUF_ADDR_FIFO_INT_EN_R {
111 BUF_ADDR_FIFO_INT_EN_R::new(((self.bits >> 13) & 1) != 0)
112 }
113 #[doc = "Bit 14 - Set an INT when the value of CSIC_DMA_STORED_FRM_CNT reaches CSIC_DMA_STORED_FRM_THRESHOLD, only use in BUF Address FIFO MODE."]
114 #[inline(always)]
115 pub fn stored_frm_cnt_int_en(&self) -> STORED_FRM_CNT_INT_EN_R {
116 STORED_FRM_CNT_INT_EN_R::new(((self.bits >> 14) & 1) != 0)
117 }
118 #[doc = "Bit 15 - Set an INT when frame starts with empty Buffer Address FIFO, only use in BUF Address FIFO MODE."]
119 #[inline(always)]
120 pub fn frm_lost_int_en(&self) -> FRM_LOST_INT_EN_R {
121 FRM_LOST_INT_EN_R::new(((self.bits >> 15) & 1) != 0)
122 }
123}
124impl W {
125 #[doc = "Bit 0 - Capture done\n\nIndicates the CSI has completed capturing the image data. For still capture, the bit is set when one frame data has been written to buffer. For video capture, the bit is set when the last frame has been written to buffer after video capture has been disabled. For CCIR656 interface, if the output format is frame planar YCbCr 420 mode, the frame end means the field2 end, the other frame end means field end."]
126 #[inline(always)]
127 #[must_use]
128 pub fn cd_int_en(&mut self) -> CD_INT_EN_W<CSIC_DMA_INT_EN_SPEC> {
129 CD_INT_EN_W::new(self, 0)
130 }
131 #[doc = "Bit 1 - Frame done\n\nIndicates the CSI has finished capturing an image frame. Applies to video capture mode. The bit is set after each completed frame capturing data is written to buffer as long as video capture remains enabled."]
132 #[inline(always)]
133 #[must_use]
134 pub fn fd_int_en(&mut self) -> FD_INT_EN_W<CSIC_DMA_INT_EN_SPEC> {
135 FD_INT_EN_W::new(self, 1)
136 }
137 #[doc = "Bit 2 - FIFO 0 overflow\n\nThe bit is set when the FIFO 0 became overflow."]
138 #[inline(always)]
139 #[must_use]
140 pub fn fifo0_of_int_en(&mut self) -> FIFO0_OF_INT_EN_W<CSIC_DMA_INT_EN_SPEC> {
141 FIFO0_OF_INT_EN_W::new(self, 2)
142 }
143 #[doc = "Bit 3 - FIFO 1 overflow\n\nThe bit is set when the FIFO 1 became overflow."]
144 #[inline(always)]
145 #[must_use]
146 pub fn fifo1_of_int_en(&mut self) -> FIFO1_OF_INT_EN_W<CSIC_DMA_INT_EN_SPEC> {
147 FIFO1_OF_INT_EN_W::new(self, 3)
148 }
149 #[doc = "Bit 4 - FIFO 2 overflow\n\nThe bit is set when the FIFO 2 became overflow."]
150 #[inline(always)]
151 #[must_use]
152 pub fn fifo2_of_int_en(&mut self) -> FIFO2_OF_INT_EN_W<CSIC_DMA_INT_EN_SPEC> {
153 FIFO2_OF_INT_EN_W::new(self, 4)
154 }
155 #[doc = "Bit 5 - Line counter flag The bit is set when the specific line has been written to dram every frame. The line number is set in the line counter register."]
156 #[inline(always)]
157 #[must_use]
158 pub fn lc_int_en(&mut self) -> LC_INT_EN_W<CSIC_DMA_INT_EN_SPEC> {
159 LC_INT_EN_W::new(self, 5)
160 }
161 #[doc = "Bit 6 - Hblank FIFO overflow The bit is set when 3 FIFOs still overflow after the hblank."]
162 #[inline(always)]
163 #[must_use]
164 pub fn hb_of_int_en(&mut self) -> HB_OF_INT_EN_W<CSIC_DMA_INT_EN_SPEC> {
165 HB_OF_INT_EN_W::new(self, 6)
166 }
167 #[doc = "Bit 7 - vsync flag\n\nThe bit is set when vsync come. And at this time load the buffer address for the coming frame. So after this irq come, changing the buffer address could only effect next frame"]
168 #[inline(always)]
169 #[must_use]
170 pub fn vs_int_en(&mut self) -> VS_INT_EN_W<CSIC_DMA_INT_EN_SPEC> {
171 VS_INT_EN_W::new(self, 7)
172 }
173 #[doc = "Bit 11 - Set a INT when clear Frame cnt."]
174 #[inline(always)]
175 #[must_use]
176 pub fn clr_frame_cnt_int_en(&mut self) -> CLR_FRAME_CNT_INT_EN_W<CSIC_DMA_INT_EN_SPEC> {
177 CLR_FRAME_CNT_INT_EN_W::new(self, 11)
178 }
179 #[doc = "Bit 12 - Set an INT when no video input exceeds the setting threshold time"]
180 #[inline(always)]
181 #[must_use]
182 pub fn video_input_to_int_en(&mut self) -> VIDEO_INPUT_TO_INT_EN_W<CSIC_DMA_INT_EN_SPEC> {
183 VIDEO_INPUT_TO_INT_EN_W::new(self, 12)
184 }
185 #[doc = "Bit 13 - Set an INT when content in BUF Address FIFO less than CSIC_DMA_BUFA_FIFO_THRESHOLD, only use in BUF Address FIFO MODE."]
186 #[inline(always)]
187 #[must_use]
188 pub fn buf_addr_fifo_int_en(&mut self) -> BUF_ADDR_FIFO_INT_EN_W<CSIC_DMA_INT_EN_SPEC> {
189 BUF_ADDR_FIFO_INT_EN_W::new(self, 13)
190 }
191 #[doc = "Bit 14 - Set an INT when the value of CSIC_DMA_STORED_FRM_CNT reaches CSIC_DMA_STORED_FRM_THRESHOLD, only use in BUF Address FIFO MODE."]
192 #[inline(always)]
193 #[must_use]
194 pub fn stored_frm_cnt_int_en(&mut self) -> STORED_FRM_CNT_INT_EN_W<CSIC_DMA_INT_EN_SPEC> {
195 STORED_FRM_CNT_INT_EN_W::new(self, 14)
196 }
197 #[doc = "Bit 15 - Set an INT when frame starts with empty Buffer Address FIFO, only use in BUF Address FIFO MODE."]
198 #[inline(always)]
199 #[must_use]
200 pub fn frm_lost_int_en(&mut self) -> FRM_LOST_INT_EN_W<CSIC_DMA_INT_EN_SPEC> {
201 FRM_LOST_INT_EN_W::new(self, 15)
202 }
203 #[doc = r" Writes raw bits to the register."]
204 #[doc = r""]
205 #[doc = r" # Safety"]
206 #[doc = r""]
207 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
208 #[inline(always)]
209 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
210 self.bits = bits;
211 self
212 }
213}
214#[doc = "CSIC DMA Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csic_dma_int_en::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csic_dma_int_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
215pub struct CSIC_DMA_INT_EN_SPEC;
216impl crate::RegisterSpec for CSIC_DMA_INT_EN_SPEC {
217 type Ux = u32;
218}
219#[doc = "`read()` method returns [`csic_dma_int_en::R`](R) reader structure"]
220impl crate::Readable for CSIC_DMA_INT_EN_SPEC {}
221#[doc = "`write(|w| ..)` method takes [`csic_dma_int_en::W`](W) writer structure"]
222impl crate::Writable for CSIC_DMA_INT_EN_SPEC {
223 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
224 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
225}
226#[doc = "`reset()` method sets csic_dma_int_en to value 0"]
227impl crate::Resettable for CSIC_DMA_INT_EN_SPEC {
228 const RESET_VALUE: Self::Ux = 0;
229}