d1_pac/csic/csic_dma/
csic_dma_flip_size.rs

1#[doc = "Register `csic_dma_flip_size` reader"]
2pub type R = crate::R<CSIC_DMA_FLIP_SIZE_SPEC>;
3#[doc = "Register `csic_dma_flip_size` writer"]
4pub type W = crate::W<CSIC_DMA_FLIP_SIZE_SPEC>;
5#[doc = "Field `valid_len` reader - Valid components of a line when in HFLIP mode. Unit is pixel component.\n\nOnly Readable when FLIP_SIZE_CFG_MODE is set to 0."]
6pub type VALID_LEN_R = crate::FieldReader<u16>;
7#[doc = "Field `valid_len` writer - Valid components of a line when in HFLIP mode. Unit is pixel component.\n\nOnly Readable when FLIP_SIZE_CFG_MODE is set to 0."]
8pub type VALID_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
9#[doc = "Field `ver_len` reader - Vertical line number when in VFLIP mode. Unit is line.\n\nOnly Readable when FLIP_SIZE_CFG_MODE is set to 0."]
10pub type VER_LEN_R = crate::FieldReader<u16>;
11#[doc = "Field `ver_len` writer - Vertical line number when in VFLIP mode. Unit is line.\n\nOnly Readable when FLIP_SIZE_CFG_MODE is set to 0."]
12pub type VER_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
13impl R {
14    #[doc = "Bits 0:13 - Valid components of a line when in HFLIP mode. Unit is pixel component.\n\nOnly Readable when FLIP_SIZE_CFG_MODE is set to 0."]
15    #[inline(always)]
16    pub fn valid_len(&self) -> VALID_LEN_R {
17        VALID_LEN_R::new((self.bits & 0x3fff) as u16)
18    }
19    #[doc = "Bits 16:28 - Vertical line number when in VFLIP mode. Unit is line.\n\nOnly Readable when FLIP_SIZE_CFG_MODE is set to 0."]
20    #[inline(always)]
21    pub fn ver_len(&self) -> VER_LEN_R {
22        VER_LEN_R::new(((self.bits >> 16) & 0x1fff) as u16)
23    }
24}
25impl W {
26    #[doc = "Bits 0:13 - Valid components of a line when in HFLIP mode. Unit is pixel component.\n\nOnly Readable when FLIP_SIZE_CFG_MODE is set to 0."]
27    #[inline(always)]
28    #[must_use]
29    pub fn valid_len(&mut self) -> VALID_LEN_W<CSIC_DMA_FLIP_SIZE_SPEC> {
30        VALID_LEN_W::new(self, 0)
31    }
32    #[doc = "Bits 16:28 - Vertical line number when in VFLIP mode. Unit is line.\n\nOnly Readable when FLIP_SIZE_CFG_MODE is set to 0."]
33    #[inline(always)]
34    #[must_use]
35    pub fn ver_len(&mut self) -> VER_LEN_W<CSIC_DMA_FLIP_SIZE_SPEC> {
36        VER_LEN_W::new(self, 16)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "CSIC DMA Flip Size Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csic_dma_flip_size::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csic_dma_flip_size::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
50pub struct CSIC_DMA_FLIP_SIZE_SPEC;
51impl crate::RegisterSpec for CSIC_DMA_FLIP_SIZE_SPEC {
52    type Ux = u32;
53}
54#[doc = "`read()` method returns [`csic_dma_flip_size::R`](R) reader structure"]
55impl crate::Readable for CSIC_DMA_FLIP_SIZE_SPEC {}
56#[doc = "`write(|w| ..)` method takes [`csic_dma_flip_size::W`](W) writer structure"]
57impl crate::Writable for CSIC_DMA_FLIP_SIZE_SPEC {
58    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
59    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
60}
61#[doc = "`reset()` method sets csic_dma_flip_size to value 0x02d0_0500"]
62impl crate::Resettable for CSIC_DMA_FLIP_SIZE_SPEC {
63    const RESET_VALUE: Self::Ux = 0x02d0_0500;
64}
d1_pac/csic/csic_dma/csic_dma_flip_size.rs

d1_pac/csic/csic_dma/
csic_dma_flip_size.rs
