d1_pac/csic/csic_dma/
csic_dma_f0_bufa_result.rs

1#[doc = "Register `csic_dma_f0_bufa_result` reader"]
2pub type R = crate::R<CSIC_DMA_F0_BUFA_RESULT_SPEC>;
3#[doc = "Register `csic_dma_f0_bufa_result` writer"]
4pub type W = crate::W<CSIC_DMA_F0_BUFA_RESULT_SPEC>;
5#[doc = "Field `f0_bufa_result` reader - Indicate the final F0_BUFA address used for DMA or FBC after software configuration or hardware calculation from Buffer-A address register or buffer address fifo. Only used for debug."]
6pub type F0_BUFA_RESULT_R = crate::FieldReader<u32>;
7impl R {
8    #[doc = "Bits 0:31 - Indicate the final F0_BUFA address used for DMA or FBC after software configuration or hardware calculation from Buffer-A address register or buffer address fifo. Only used for debug."]
9    #[inline(always)]
10    pub fn f0_bufa_result(&self) -> F0_BUFA_RESULT_R {
11        F0_BUFA_RESULT_R::new(self.bits)
12    }
13}
14impl W {
15    #[doc = r" Writes raw bits to the register."]
16    #[doc = r""]
17    #[doc = r" # Safety"]
18    #[doc = r""]
19    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
20    #[inline(always)]
21    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
22        self.bits = bits;
23        self
24    }
25}
26#[doc = "CSIC DMA FIFO 0 Output Buffer-A Address Result Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csic_dma_f0_bufa_result::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csic_dma_f0_bufa_result::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
27pub struct CSIC_DMA_F0_BUFA_RESULT_SPEC;
28impl crate::RegisterSpec for CSIC_DMA_F0_BUFA_RESULT_SPEC {
29    type Ux = u32;
30}
31#[doc = "`read()` method returns [`csic_dma_f0_bufa_result::R`](R) reader structure"]
32impl crate::Readable for CSIC_DMA_F0_BUFA_RESULT_SPEC {}
33#[doc = "`write(|w| ..)` method takes [`csic_dma_f0_bufa_result::W`](W) writer structure"]
34impl crate::Writable for CSIC_DMA_F0_BUFA_RESULT_SPEC {
35    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
36    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
37}
38#[doc = "`reset()` method sets csic_dma_f0_bufa_result to value 0"]
39impl crate::Resettable for CSIC_DMA_F0_BUFA_RESULT_SPEC {
40    const RESET_VALUE: Self::Ux = 0;
41}
d1_pac/csic/csic_dma/csic_dma_f0_bufa_result.rs

d1_pac/csic/csic_dma/
csic_dma_f0_bufa_result.rs
