d1_pac/csic/csic_dma/
csic_dma_cfg.rs

1#[doc = "Register `csic_dma_cfg` reader"]
2pub type R = crate::R<CSIC_DMA_CFG_SPEC>;
3#[doc = "Register `csic_dma_cfg` writer"]
4pub type W = crate::W<CSIC_DMA_CFG_SPEC>;
5#[doc = "Field `min_sdr_wr_size` reader - Minimum size of SDRAM block write"]
6pub type MIN_SDR_WR_SIZE_R = crate::FieldReader<MIN_SDR_WR_SIZE_A>;
7#[doc = "Minimum size of SDRAM block write\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum MIN_SDR_WR_SIZE_A {
11    #[doc = "0: 256 bytes (if hflip is enabled, always select 256 bytes)"]
12    _256 = 0,
13    #[doc = "1: 512 bytes"]
14    _512 = 1,
15    #[doc = "2: 1K bytes"]
16    _1K = 2,
17    #[doc = "3: 2K bytes"]
18    _2K = 3,
19}
20impl From<MIN_SDR_WR_SIZE_A> for u8 {
21    #[inline(always)]
22    fn from(variant: MIN_SDR_WR_SIZE_A) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for MIN_SDR_WR_SIZE_A {
27    type Ux = u8;
28}
29impl MIN_SDR_WR_SIZE_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> MIN_SDR_WR_SIZE_A {
33        match self.bits {
34            0 => MIN_SDR_WR_SIZE_A::_256,
35            1 => MIN_SDR_WR_SIZE_A::_512,
36            2 => MIN_SDR_WR_SIZE_A::_1K,
37            3 => MIN_SDR_WR_SIZE_A::_2K,
38            _ => unreachable!(),
39        }
40    }
41    #[doc = "256 bytes (if hflip is enabled, always select 256 bytes)"]
42    #[inline(always)]
43    pub fn is_256(&self) -> bool {
44        *self == MIN_SDR_WR_SIZE_A::_256
45    }
46    #[doc = "512 bytes"]
47    #[inline(always)]
48    pub fn is_512(&self) -> bool {
49        *self == MIN_SDR_WR_SIZE_A::_512
50    }
51    #[doc = "1K bytes"]
52    #[inline(always)]
53    pub fn is_1k(&self) -> bool {
54        *self == MIN_SDR_WR_SIZE_A::_1K
55    }
56    #[doc = "2K bytes"]
57    #[inline(always)]
58    pub fn is_2k(&self) -> bool {
59        *self == MIN_SDR_WR_SIZE_A::_2K
60    }
61}
62#[doc = "Field `min_sdr_wr_size` writer - Minimum size of SDRAM block write"]
63pub type MIN_SDR_WR_SIZE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, MIN_SDR_WR_SIZE_A>;
64impl<'a, REG> MIN_SDR_WR_SIZE_W<'a, REG>
65where
66    REG: crate::Writable + crate::RegisterSpec,
67    REG::Ux: From<u8>,
68{
69    #[doc = "256 bytes (if hflip is enabled, always select 256 bytes)"]
70    #[inline(always)]
71    pub fn _256(self) -> &'a mut crate::W<REG> {
72        self.variant(MIN_SDR_WR_SIZE_A::_256)
73    }
74    #[doc = "512 bytes"]
75    #[inline(always)]
76    pub fn _512(self) -> &'a mut crate::W<REG> {
77        self.variant(MIN_SDR_WR_SIZE_A::_512)
78    }
79    #[doc = "1K bytes"]
80    #[inline(always)]
81    pub fn _1k(self) -> &'a mut crate::W<REG> {
82        self.variant(MIN_SDR_WR_SIZE_A::_1K)
83    }
84    #[doc = "2K bytes"]
85    #[inline(always)]
86    pub fn _2k(self) -> &'a mut crate::W<REG> {
87        self.variant(MIN_SDR_WR_SIZE_A::_2K)
88    }
89}
90#[doc = "Field `fps_ds` reader - Fps down sample"]
91pub type FPS_DS_R = crate::FieldReader<FPS_DS_A>;
92#[doc = "Fps down sample\n\nValue on reset: 0"]
93#[derive(Clone, Copy, Debug, PartialEq, Eq)]
94#[repr(u8)]
95pub enum FPS_DS_A {
96    #[doc = "0: no down sample"]
97    NO_DOWN_SAMPLE = 0,
98    #[doc = "2: 1/3 fps, only receives the first frame every 3 frames"]
99    _1_3 = 2,
100    #[doc = "3: 1/4 fps, only receives the first frame every 4 frames"]
101    _1_4 = 3,
102    #[doc = "4: 1/5 fps, only receives the first frame every 5 frames"]
103    _1_5 = 4,
104    #[doc = "5: 1/6 fps, only receives the first frame every 6 frames"]
105    _1_6 = 5,
106    #[doc = "6: 1/7 fps, only receives the first frame every 7 frames"]
107    _1_7 = 6,
108    #[doc = "7: 1/8 fps, only receives the first frame every 8 frames"]
109    _1_8 = 7,
110    #[doc = "8: 1/9 fps, only receives the first frame every 9 frames"]
111    _1_9 = 8,
112    #[doc = "9: 1/10 fps, only receives the first frame every 10 frames"]
113    _1_10 = 9,
114    #[doc = "10: 1/11 fps, only receives the first frame every 11 frames"]
115    _1_11 = 10,
116    #[doc = "11: 1/12 fps, only receives the first frame every 12 frames"]
117    _1_12 = 11,
118    #[doc = "12: 1/13 fps, only receives the first frame every 13 frames"]
119    _1_13 = 12,
120    #[doc = "13: 1/14 fps, only receives the first frame every 14 frames"]
121    _1_14 = 13,
122    #[doc = "14: 1/15 fps, only receives the first frame every 15 frames"]
123    _1_15 = 14,
124    #[doc = "15: 1/16 fps, only receives the first frame every 16 frames"]
125    _1_16 = 15,
126}
127impl From<FPS_DS_A> for u8 {
128    #[inline(always)]
129    fn from(variant: FPS_DS_A) -> Self {
130        variant as _
131    }
132}
133impl crate::FieldSpec for FPS_DS_A {
134    type Ux = u8;
135}
136impl FPS_DS_R {
137    #[doc = "Get enumerated values variant"]
138    #[inline(always)]
139    pub const fn variant(&self) -> Option<FPS_DS_A> {
140        match self.bits {
141            0 => Some(FPS_DS_A::NO_DOWN_SAMPLE),
142            2 => Some(FPS_DS_A::_1_3),
143            3 => Some(FPS_DS_A::_1_4),
144            4 => Some(FPS_DS_A::_1_5),
145            5 => Some(FPS_DS_A::_1_6),
146            6 => Some(FPS_DS_A::_1_7),
147            7 => Some(FPS_DS_A::_1_8),
148            8 => Some(FPS_DS_A::_1_9),
149            9 => Some(FPS_DS_A::_1_10),
150            10 => Some(FPS_DS_A::_1_11),
151            11 => Some(FPS_DS_A::_1_12),
152            12 => Some(FPS_DS_A::_1_13),
153            13 => Some(FPS_DS_A::_1_14),
154            14 => Some(FPS_DS_A::_1_15),
155            15 => Some(FPS_DS_A::_1_16),
156            _ => None,
157        }
158    }
159    #[doc = "no down sample"]
160    #[inline(always)]
161    pub fn is_no_down_sample(&self) -> bool {
162        *self == FPS_DS_A::NO_DOWN_SAMPLE
163    }
164    #[doc = "1/3 fps, only receives the first frame every 3 frames"]
165    #[inline(always)]
166    pub fn is_1_3(&self) -> bool {
167        *self == FPS_DS_A::_1_3
168    }
169    #[doc = "1/4 fps, only receives the first frame every 4 frames"]
170    #[inline(always)]
171    pub fn is_1_4(&self) -> bool {
172        *self == FPS_DS_A::_1_4
173    }
174    #[doc = "1/5 fps, only receives the first frame every 5 frames"]
175    #[inline(always)]
176    pub fn is_1_5(&self) -> bool {
177        *self == FPS_DS_A::_1_5
178    }
179    #[doc = "1/6 fps, only receives the first frame every 6 frames"]
180    #[inline(always)]
181    pub fn is_1_6(&self) -> bool {
182        *self == FPS_DS_A::_1_6
183    }
184    #[doc = "1/7 fps, only receives the first frame every 7 frames"]
185    #[inline(always)]
186    pub fn is_1_7(&self) -> bool {
187        *self == FPS_DS_A::_1_7
188    }
189    #[doc = "1/8 fps, only receives the first frame every 8 frames"]
190    #[inline(always)]
191    pub fn is_1_8(&self) -> bool {
192        *self == FPS_DS_A::_1_8
193    }
194    #[doc = "1/9 fps, only receives the first frame every 9 frames"]
195    #[inline(always)]
196    pub fn is_1_9(&self) -> bool {
197        *self == FPS_DS_A::_1_9
198    }
199    #[doc = "1/10 fps, only receives the first frame every 10 frames"]
200    #[inline(always)]
201    pub fn is_1_10(&self) -> bool {
202        *self == FPS_DS_A::_1_10
203    }
204    #[doc = "1/11 fps, only receives the first frame every 11 frames"]
205    #[inline(always)]
206    pub fn is_1_11(&self) -> bool {
207        *self == FPS_DS_A::_1_11
208    }
209    #[doc = "1/12 fps, only receives the first frame every 12 frames"]
210    #[inline(always)]
211    pub fn is_1_12(&self) -> bool {
212        *self == FPS_DS_A::_1_12
213    }
214    #[doc = "1/13 fps, only receives the first frame every 13 frames"]
215    #[inline(always)]
216    pub fn is_1_13(&self) -> bool {
217        *self == FPS_DS_A::_1_13
218    }
219    #[doc = "1/14 fps, only receives the first frame every 14 frames"]
220    #[inline(always)]
221    pub fn is_1_14(&self) -> bool {
222        *self == FPS_DS_A::_1_14
223    }
224    #[doc = "1/15 fps, only receives the first frame every 15 frames"]
225    #[inline(always)]
226    pub fn is_1_15(&self) -> bool {
227        *self == FPS_DS_A::_1_15
228    }
229    #[doc = "1/16 fps, only receives the first frame every 16 frames"]
230    #[inline(always)]
231    pub fn is_1_16(&self) -> bool {
232        *self == FPS_DS_A::_1_16
233    }
234}
235#[doc = "Field `fps_ds` writer - Fps down sample"]
236pub type FPS_DS_W<'a, REG> = crate::FieldWriter<'a, REG, 4, FPS_DS_A>;
237impl<'a, REG> FPS_DS_W<'a, REG>
238where
239    REG: crate::Writable + crate::RegisterSpec,
240    REG::Ux: From<u8>,
241{
242    #[doc = "no down sample"]
243    #[inline(always)]
244    pub fn no_down_sample(self) -> &'a mut crate::W<REG> {
245        self.variant(FPS_DS_A::NO_DOWN_SAMPLE)
246    }
247    #[doc = "1/3 fps, only receives the first frame every 3 frames"]
248    #[inline(always)]
249    pub fn _1_3(self) -> &'a mut crate::W<REG> {
250        self.variant(FPS_DS_A::_1_3)
251    }
252    #[doc = "1/4 fps, only receives the first frame every 4 frames"]
253    #[inline(always)]
254    pub fn _1_4(self) -> &'a mut crate::W<REG> {
255        self.variant(FPS_DS_A::_1_4)
256    }
257    #[doc = "1/5 fps, only receives the first frame every 5 frames"]
258    #[inline(always)]
259    pub fn _1_5(self) -> &'a mut crate::W<REG> {
260        self.variant(FPS_DS_A::_1_5)
261    }
262    #[doc = "1/6 fps, only receives the first frame every 6 frames"]
263    #[inline(always)]
264    pub fn _1_6(self) -> &'a mut crate::W<REG> {
265        self.variant(FPS_DS_A::_1_6)
266    }
267    #[doc = "1/7 fps, only receives the first frame every 7 frames"]
268    #[inline(always)]
269    pub fn _1_7(self) -> &'a mut crate::W<REG> {
270        self.variant(FPS_DS_A::_1_7)
271    }
272    #[doc = "1/8 fps, only receives the first frame every 8 frames"]
273    #[inline(always)]
274    pub fn _1_8(self) -> &'a mut crate::W<REG> {
275        self.variant(FPS_DS_A::_1_8)
276    }
277    #[doc = "1/9 fps, only receives the first frame every 9 frames"]
278    #[inline(always)]
279    pub fn _1_9(self) -> &'a mut crate::W<REG> {
280        self.variant(FPS_DS_A::_1_9)
281    }
282    #[doc = "1/10 fps, only receives the first frame every 10 frames"]
283    #[inline(always)]
284    pub fn _1_10(self) -> &'a mut crate::W<REG> {
285        self.variant(FPS_DS_A::_1_10)
286    }
287    #[doc = "1/11 fps, only receives the first frame every 11 frames"]
288    #[inline(always)]
289    pub fn _1_11(self) -> &'a mut crate::W<REG> {
290        self.variant(FPS_DS_A::_1_11)
291    }
292    #[doc = "1/12 fps, only receives the first frame every 12 frames"]
293    #[inline(always)]
294    pub fn _1_12(self) -> &'a mut crate::W<REG> {
295        self.variant(FPS_DS_A::_1_12)
296    }
297    #[doc = "1/13 fps, only receives the first frame every 13 frames"]
298    #[inline(always)]
299    pub fn _1_13(self) -> &'a mut crate::W<REG> {
300        self.variant(FPS_DS_A::_1_13)
301    }
302    #[doc = "1/14 fps, only receives the first frame every 14 frames"]
303    #[inline(always)]
304    pub fn _1_14(self) -> &'a mut crate::W<REG> {
305        self.variant(FPS_DS_A::_1_14)
306    }
307    #[doc = "1/15 fps, only receives the first frame every 15 frames"]
308    #[inline(always)]
309    pub fn _1_15(self) -> &'a mut crate::W<REG> {
310        self.variant(FPS_DS_A::_1_15)
311    }
312    #[doc = "1/16 fps, only receives the first frame every 16 frames"]
313    #[inline(always)]
314    pub fn _1_16(self) -> &'a mut crate::W<REG> {
315        self.variant(FPS_DS_A::_1_16)
316    }
317}
318#[doc = "Field `field_sel` reader - Field selection"]
319pub type FIELD_SEL_R = crate::FieldReader<FIELD_SEL_A>;
320#[doc = "Field selection\n\nValue on reset: 0"]
321#[derive(Clone, Copy, Debug, PartialEq, Eq)]
322#[repr(u8)]
323pub enum FIELD_SEL_A {
324    #[doc = "0: Capturing with field 0"]
325    FIELD_0 = 0,
326    #[doc = "1: Capturing with field 1"]
327    FIELD_1 = 1,
328    #[doc = "2: Capturing with either field"]
329    EITHER_FIELD = 2,
330}
331impl From<FIELD_SEL_A> for u8 {
332    #[inline(always)]
333    fn from(variant: FIELD_SEL_A) -> Self {
334        variant as _
335    }
336}
337impl crate::FieldSpec for FIELD_SEL_A {
338    type Ux = u8;
339}
340impl FIELD_SEL_R {
341    #[doc = "Get enumerated values variant"]
342    #[inline(always)]
343    pub const fn variant(&self) -> Option<FIELD_SEL_A> {
344        match self.bits {
345            0 => Some(FIELD_SEL_A::FIELD_0),
346            1 => Some(FIELD_SEL_A::FIELD_1),
347            2 => Some(FIELD_SEL_A::EITHER_FIELD),
348            _ => None,
349        }
350    }
351    #[doc = "Capturing with field 0"]
352    #[inline(always)]
353    pub fn is_field_0(&self) -> bool {
354        *self == FIELD_SEL_A::FIELD_0
355    }
356    #[doc = "Capturing with field 1"]
357    #[inline(always)]
358    pub fn is_field_1(&self) -> bool {
359        *self == FIELD_SEL_A::FIELD_1
360    }
361    #[doc = "Capturing with either field"]
362    #[inline(always)]
363    pub fn is_either_field(&self) -> bool {
364        *self == FIELD_SEL_A::EITHER_FIELD
365    }
366}
367#[doc = "Field `field_sel` writer - Field selection"]
368pub type FIELD_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, FIELD_SEL_A>;
369impl<'a, REG> FIELD_SEL_W<'a, REG>
370where
371    REG: crate::Writable + crate::RegisterSpec,
372    REG::Ux: From<u8>,
373{
374    #[doc = "Capturing with field 0"]
375    #[inline(always)]
376    pub fn field_0(self) -> &'a mut crate::W<REG> {
377        self.variant(FIELD_SEL_A::FIELD_0)
378    }
379    #[doc = "Capturing with field 1"]
380    #[inline(always)]
381    pub fn field_1(self) -> &'a mut crate::W<REG> {
382        self.variant(FIELD_SEL_A::FIELD_1)
383    }
384    #[doc = "Capturing with either field"]
385    #[inline(always)]
386    pub fn either_field(self) -> &'a mut crate::W<REG> {
387        self.variant(FIELD_SEL_A::EITHER_FIELD)
388    }
389}
390#[doc = "Field `hflip_en` reader - Horizontal flip enable\n\nWhen enabled, the received data will be arranged in horizontal flip."]
391pub type HFLIP_EN_R = crate::BitReader<HFLIP_EN_A>;
392#[doc = "Horizontal flip enable\n\nWhen enabled, the received data will be arranged in horizontal flip.\n\nValue on reset: 0"]
393#[derive(Clone, Copy, Debug, PartialEq, Eq)]
394pub enum HFLIP_EN_A {
395    #[doc = "0: Disable"]
396    DISABLE = 0,
397    #[doc = "1: Enable"]
398    ENABLE = 1,
399}
400impl From<HFLIP_EN_A> for bool {
401    #[inline(always)]
402    fn from(variant: HFLIP_EN_A) -> Self {
403        variant as u8 != 0
404    }
405}
406impl HFLIP_EN_R {
407    #[doc = "Get enumerated values variant"]
408    #[inline(always)]
409    pub const fn variant(&self) -> HFLIP_EN_A {
410        match self.bits {
411            false => HFLIP_EN_A::DISABLE,
412            true => HFLIP_EN_A::ENABLE,
413        }
414    }
415    #[doc = "Disable"]
416    #[inline(always)]
417    pub fn is_disable(&self) -> bool {
418        *self == HFLIP_EN_A::DISABLE
419    }
420    #[doc = "Enable"]
421    #[inline(always)]
422    pub fn is_enable(&self) -> bool {
423        *self == HFLIP_EN_A::ENABLE
424    }
425}
426#[doc = "Field `hflip_en` writer - Horizontal flip enable\n\nWhen enabled, the received data will be arranged in horizontal flip."]
427pub type HFLIP_EN_W<'a, REG> = crate::BitWriter<'a, REG, HFLIP_EN_A>;
428impl<'a, REG> HFLIP_EN_W<'a, REG>
429where
430    REG: crate::Writable + crate::RegisterSpec,
431{
432    #[doc = "Disable"]
433    #[inline(always)]
434    pub fn disable(self) -> &'a mut crate::W<REG> {
435        self.variant(HFLIP_EN_A::DISABLE)
436    }
437    #[doc = "Enable"]
438    #[inline(always)]
439    pub fn enable(self) -> &'a mut crate::W<REG> {
440        self.variant(HFLIP_EN_A::ENABLE)
441    }
442}
443#[doc = "Field `vflip_en` reader - Vertical flip enable\n\nWhen enabled, the received data will be arranged in vertical flip."]
444pub type VFLIP_EN_R = crate::BitReader<VFLIP_EN_A>;
445#[doc = "Vertical flip enable\n\nWhen enabled, the received data will be arranged in vertical flip.\n\nValue on reset: 0"]
446#[derive(Clone, Copy, Debug, PartialEq, Eq)]
447pub enum VFLIP_EN_A {
448    #[doc = "0: Disable"]
449    DISABLE = 0,
450    #[doc = "1: Enable"]
451    ENABLE = 1,
452}
453impl From<VFLIP_EN_A> for bool {
454    #[inline(always)]
455    fn from(variant: VFLIP_EN_A) -> Self {
456        variant as u8 != 0
457    }
458}
459impl VFLIP_EN_R {
460    #[doc = "Get enumerated values variant"]
461    #[inline(always)]
462    pub const fn variant(&self) -> VFLIP_EN_A {
463        match self.bits {
464            false => VFLIP_EN_A::DISABLE,
465            true => VFLIP_EN_A::ENABLE,
466        }
467    }
468    #[doc = "Disable"]
469    #[inline(always)]
470    pub fn is_disable(&self) -> bool {
471        *self == VFLIP_EN_A::DISABLE
472    }
473    #[doc = "Enable"]
474    #[inline(always)]
475    pub fn is_enable(&self) -> bool {
476        *self == VFLIP_EN_A::ENABLE
477    }
478}
479#[doc = "Field `vflip_en` writer - Vertical flip enable\n\nWhen enabled, the received data will be arranged in vertical flip."]
480pub type VFLIP_EN_W<'a, REG> = crate::BitWriter<'a, REG, VFLIP_EN_A>;
481impl<'a, REG> VFLIP_EN_W<'a, REG>
482where
483    REG: crate::Writable + crate::RegisterSpec,
484{
485    #[doc = "Disable"]
486    #[inline(always)]
487    pub fn disable(self) -> &'a mut crate::W<REG> {
488        self.variant(VFLIP_EN_A::DISABLE)
489    }
490    #[doc = "Enable"]
491    #[inline(always)]
492    pub fn enable(self) -> &'a mut crate::W<REG> {
493        self.variant(VFLIP_EN_A::ENABLE)
494    }
495}
496#[doc = "Field `output_fmt` reader - Output data format\n\nWhen the input format is set to RAW stream\n\n0000: field-raw-8\n\n0001: field-raw-10\n\n0010: field-raw-12\n\n0011: reserved\n\n0100: field-rgb565\n\n0101: field-rgb888\n\n0110: field-prgb888\n\n0111: reserved\n\n1000: frame-raw-8\n\n1001: frame-raw-10\n\n1010: frame-raw-12\n\n1011: reserved\n\n1100: frame-rgb565\n\n1101: frame-rgb888\n\n1110: frame-prgb888\n\n1111: reserved\n\nWhen the input format is set to YUV422\n\n0000: field planar YCbCr 422\n\n0001: field planar YCbCr 420\n\n0010: frame planar YCbCr 420\n\n0011: frame planar YCbCr 422\n\n0100: field planar YCbCr 422 UV combined (UV sequence)\n\n0101: field planar YCbCr 420 UV combined (UV sequence)\n\n0110: frame planar YCbCr 420 UV combined (UV sequence)\n\n0111: frame planar YCbCr 422 UV combined (UV sequence)\n\n1000: filed planar YCbCr 422 UV combined (VU sequence)\n\n1001: field planar YCbCr 420 UV combined (VU sequence)\n\n1010: frame planar YCbCr 420 UV combined (VU sequence)\n\n1011: frame planar YCbCr 422 UV combined (VU sequence)\n\n1100: reserved\n\n1101: field YCbCr 400\n\n1110: reserved\n\n1111: frame YCbCr 400\n\nWhen the input format is set to YUV420\n\n0000: reserved\n\n0001: field planar YCbCr 420\n\n0010: frame planar YCbCr 420\n\n0011: reserved\n\n0100: reserved\n\n0101: field planar YCbCr 420 UV combined (UV sequence)\n\n0110: frame planar YCbCr 420 UV combined (UV sequence) 0111~1000: reserved\n\n1001: field planar YCbCr 420 UV combined (VU sequence)\n\n1010: frame planar YCbCr 420 UV combined (VU sequence) 1011~1100: reserved\n\n1101: field YCbCr 400\n\n1110: reserved\n\n1111: frame YCbCr 400"]
497pub type OUTPUT_FMT_R = crate::FieldReader;
498#[doc = "Field `output_fmt` writer - Output data format\n\nWhen the input format is set to RAW stream\n\n0000: field-raw-8\n\n0001: field-raw-10\n\n0010: field-raw-12\n\n0011: reserved\n\n0100: field-rgb565\n\n0101: field-rgb888\n\n0110: field-prgb888\n\n0111: reserved\n\n1000: frame-raw-8\n\n1001: frame-raw-10\n\n1010: frame-raw-12\n\n1011: reserved\n\n1100: frame-rgb565\n\n1101: frame-rgb888\n\n1110: frame-prgb888\n\n1111: reserved\n\nWhen the input format is set to YUV422\n\n0000: field planar YCbCr 422\n\n0001: field planar YCbCr 420\n\n0010: frame planar YCbCr 420\n\n0011: frame planar YCbCr 422\n\n0100: field planar YCbCr 422 UV combined (UV sequence)\n\n0101: field planar YCbCr 420 UV combined (UV sequence)\n\n0110: frame planar YCbCr 420 UV combined (UV sequence)\n\n0111: frame planar YCbCr 422 UV combined (UV sequence)\n\n1000: filed planar YCbCr 422 UV combined (VU sequence)\n\n1001: field planar YCbCr 420 UV combined (VU sequence)\n\n1010: frame planar YCbCr 420 UV combined (VU sequence)\n\n1011: frame planar YCbCr 422 UV combined (VU sequence)\n\n1100: reserved\n\n1101: field YCbCr 400\n\n1110: reserved\n\n1111: frame YCbCr 400\n\nWhen the input format is set to YUV420\n\n0000: reserved\n\n0001: field planar YCbCr 420\n\n0010: frame planar YCbCr 420\n\n0011: reserved\n\n0100: reserved\n\n0101: field planar YCbCr 420 UV combined (UV sequence)\n\n0110: frame planar YCbCr 420 UV combined (UV sequence) 0111~1000: reserved\n\n1001: field planar YCbCr 420 UV combined (VU sequence)\n\n1010: frame planar YCbCr 420 UV combined (VU sequence) 1011~1100: reserved\n\n1101: field YCbCr 400\n\n1110: reserved\n\n1111: frame YCbCr 400"]
499pub type OUTPUT_FMT_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
500#[doc = "Field `yuv_10bit_store_configuration` reader - 10-bit store configuration"]
501pub type YUV_10BIT_STORE_CONFIGURATION_R = crate::BitReader<YUV_10BIT_STORE_CONFIGURATION_A>;
502#[doc = "10-bit store configuration\n\nValue on reset: 0"]
503#[derive(Clone, Copy, Debug, PartialEq, Eq)]
504pub enum YUV_10BIT_STORE_CONFIGURATION_A {
505    #[doc = "0: YUV 10-bit stored in low 10-bit of a 16-bit word"]
506    LOW = 0,
507    #[doc = "1: YUV 10-bit stored in high 10-bit of a 16-bit word"]
508    HIGH = 1,
509}
510impl From<YUV_10BIT_STORE_CONFIGURATION_A> for bool {
511    #[inline(always)]
512    fn from(variant: YUV_10BIT_STORE_CONFIGURATION_A) -> Self {
513        variant as u8 != 0
514    }
515}
516impl YUV_10BIT_STORE_CONFIGURATION_R {
517    #[doc = "Get enumerated values variant"]
518    #[inline(always)]
519    pub const fn variant(&self) -> YUV_10BIT_STORE_CONFIGURATION_A {
520        match self.bits {
521            false => YUV_10BIT_STORE_CONFIGURATION_A::LOW,
522            true => YUV_10BIT_STORE_CONFIGURATION_A::HIGH,
523        }
524    }
525    #[doc = "YUV 10-bit stored in low 10-bit of a 16-bit word"]
526    #[inline(always)]
527    pub fn is_low(&self) -> bool {
528        *self == YUV_10BIT_STORE_CONFIGURATION_A::LOW
529    }
530    #[doc = "YUV 10-bit stored in high 10-bit of a 16-bit word"]
531    #[inline(always)]
532    pub fn is_high(&self) -> bool {
533        *self == YUV_10BIT_STORE_CONFIGURATION_A::HIGH
534    }
535}
536#[doc = "Field `yuv_10bit_store_configuration` writer - 10-bit store configuration"]
537pub type YUV_10BIT_STORE_CONFIGURATION_W<'a, REG> =
538    crate::BitWriter<'a, REG, YUV_10BIT_STORE_CONFIGURATION_A>;
539impl<'a, REG> YUV_10BIT_STORE_CONFIGURATION_W<'a, REG>
540where
541    REG: crate::Writable + crate::RegisterSpec,
542{
543    #[doc = "YUV 10-bit stored in low 10-bit of a 16-bit word"]
544    #[inline(always)]
545    pub fn low(self) -> &'a mut crate::W<REG> {
546        self.variant(YUV_10BIT_STORE_CONFIGURATION_A::LOW)
547    }
548    #[doc = "YUV 10-bit stored in high 10-bit of a 16-bit word"]
549    #[inline(always)]
550    pub fn high(self) -> &'a mut crate::W<REG> {
551        self.variant(YUV_10BIT_STORE_CONFIGURATION_A::HIGH)
552    }
553}
554#[doc = "Field `yuv_10bit_cut_8bit` reader - 10-bit input cut to 8-bit"]
555pub type YUV_10BIT_CUT_8BIT_R = crate::BitReader<YUV_10BIT_CUT_8BIT_A>;
556#[doc = "10-bit input cut to 8-bit\n\nValue on reset: 0"]
557#[derive(Clone, Copy, Debug, PartialEq, Eq)]
558pub enum YUV_10BIT_CUT_8BIT_A {
559    #[doc = "0: Disable"]
560    DISABLE = 0,
561    #[doc = "1: Enable"]
562    ENABLE = 1,
563}
564impl From<YUV_10BIT_CUT_8BIT_A> for bool {
565    #[inline(always)]
566    fn from(variant: YUV_10BIT_CUT_8BIT_A) -> Self {
567        variant as u8 != 0
568    }
569}
570impl YUV_10BIT_CUT_8BIT_R {
571    #[doc = "Get enumerated values variant"]
572    #[inline(always)]
573    pub const fn variant(&self) -> YUV_10BIT_CUT_8BIT_A {
574        match self.bits {
575            false => YUV_10BIT_CUT_8BIT_A::DISABLE,
576            true => YUV_10BIT_CUT_8BIT_A::ENABLE,
577        }
578    }
579    #[doc = "Disable"]
580    #[inline(always)]
581    pub fn is_disable(&self) -> bool {
582        *self == YUV_10BIT_CUT_8BIT_A::DISABLE
583    }
584    #[doc = "Enable"]
585    #[inline(always)]
586    pub fn is_enable(&self) -> bool {
587        *self == YUV_10BIT_CUT_8BIT_A::ENABLE
588    }
589}
590#[doc = "Field `yuv_10bit_cut_8bit` writer - 10-bit input cut to 8-bit"]
591pub type YUV_10BIT_CUT_8BIT_W<'a, REG> = crate::BitWriter<'a, REG, YUV_10BIT_CUT_8BIT_A>;
592impl<'a, REG> YUV_10BIT_CUT_8BIT_W<'a, REG>
593where
594    REG: crate::Writable + crate::RegisterSpec,
595{
596    #[doc = "Disable"]
597    #[inline(always)]
598    pub fn disable(self) -> &'a mut crate::W<REG> {
599        self.variant(YUV_10BIT_CUT_8BIT_A::DISABLE)
600    }
601    #[doc = "Enable"]
602    #[inline(always)]
603    pub fn enable(self) -> &'a mut crate::W<REG> {
604        self.variant(YUV_10BIT_CUT_8BIT_A::ENABLE)
605    }
606}
607#[doc = "Field `pad_val` reader - Padding value when OUTPUT_FMT is prgb888\n\n0x00-0xff"]
608pub type PAD_VAL_R = crate::FieldReader;
609#[doc = "Field `pad_val` writer - Padding value when OUTPUT_FMT is prgb888\n\n0x00-0xff"]
610pub type PAD_VAL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
611impl R {
612    #[doc = "Bits 0:1 - Minimum size of SDRAM block write"]
613    #[inline(always)]
614    pub fn min_sdr_wr_size(&self) -> MIN_SDR_WR_SIZE_R {
615        MIN_SDR_WR_SIZE_R::new((self.bits & 3) as u8)
616    }
617    #[doc = "Bits 6:9 - Fps down sample"]
618    #[inline(always)]
619    pub fn fps_ds(&self) -> FPS_DS_R {
620        FPS_DS_R::new(((self.bits >> 6) & 0x0f) as u8)
621    }
622    #[doc = "Bits 10:11 - Field selection"]
623    #[inline(always)]
624    pub fn field_sel(&self) -> FIELD_SEL_R {
625        FIELD_SEL_R::new(((self.bits >> 10) & 3) as u8)
626    }
627    #[doc = "Bit 12 - Horizontal flip enable\n\nWhen enabled, the received data will be arranged in horizontal flip."]
628    #[inline(always)]
629    pub fn hflip_en(&self) -> HFLIP_EN_R {
630        HFLIP_EN_R::new(((self.bits >> 12) & 1) != 0)
631    }
632    #[doc = "Bit 13 - Vertical flip enable\n\nWhen enabled, the received data will be arranged in vertical flip."]
633    #[inline(always)]
634    pub fn vflip_en(&self) -> VFLIP_EN_R {
635        VFLIP_EN_R::new(((self.bits >> 13) & 1) != 0)
636    }
637    #[doc = "Bits 16:19 - Output data format\n\nWhen the input format is set to RAW stream\n\n0000: field-raw-8\n\n0001: field-raw-10\n\n0010: field-raw-12\n\n0011: reserved\n\n0100: field-rgb565\n\n0101: field-rgb888\n\n0110: field-prgb888\n\n0111: reserved\n\n1000: frame-raw-8\n\n1001: frame-raw-10\n\n1010: frame-raw-12\n\n1011: reserved\n\n1100: frame-rgb565\n\n1101: frame-rgb888\n\n1110: frame-prgb888\n\n1111: reserved\n\nWhen the input format is set to YUV422\n\n0000: field planar YCbCr 422\n\n0001: field planar YCbCr 420\n\n0010: frame planar YCbCr 420\n\n0011: frame planar YCbCr 422\n\n0100: field planar YCbCr 422 UV combined (UV sequence)\n\n0101: field planar YCbCr 420 UV combined (UV sequence)\n\n0110: frame planar YCbCr 420 UV combined (UV sequence)\n\n0111: frame planar YCbCr 422 UV combined (UV sequence)\n\n1000: filed planar YCbCr 422 UV combined (VU sequence)\n\n1001: field planar YCbCr 420 UV combined (VU sequence)\n\n1010: frame planar YCbCr 420 UV combined (VU sequence)\n\n1011: frame planar YCbCr 422 UV combined (VU sequence)\n\n1100: reserved\n\n1101: field YCbCr 400\n\n1110: reserved\n\n1111: frame YCbCr 400\n\nWhen the input format is set to YUV420\n\n0000: reserved\n\n0001: field planar YCbCr 420\n\n0010: frame planar YCbCr 420\n\n0011: reserved\n\n0100: reserved\n\n0101: field planar YCbCr 420 UV combined (UV sequence)\n\n0110: frame planar YCbCr 420 UV combined (UV sequence) 0111~1000: reserved\n\n1001: field planar YCbCr 420 UV combined (VU sequence)\n\n1010: frame planar YCbCr 420 UV combined (VU sequence) 1011~1100: reserved\n\n1101: field YCbCr 400\n\n1110: reserved\n\n1111: frame YCbCr 400"]
638    #[inline(always)]
639    pub fn output_fmt(&self) -> OUTPUT_FMT_R {
640        OUTPUT_FMT_R::new(((self.bits >> 16) & 0x0f) as u8)
641    }
642    #[doc = "Bit 20 - 10-bit store configuration"]
643    #[inline(always)]
644    pub fn yuv_10bit_store_configuration(&self) -> YUV_10BIT_STORE_CONFIGURATION_R {
645        YUV_10BIT_STORE_CONFIGURATION_R::new(((self.bits >> 20) & 1) != 0)
646    }
647    #[doc = "Bit 21 - 10-bit input cut to 8-bit"]
648    #[inline(always)]
649    pub fn yuv_10bit_cut_8bit(&self) -> YUV_10BIT_CUT_8BIT_R {
650        YUV_10BIT_CUT_8BIT_R::new(((self.bits >> 21) & 1) != 0)
651    }
652    #[doc = "Bits 24:31 - Padding value when OUTPUT_FMT is prgb888\n\n0x00-0xff"]
653    #[inline(always)]
654    pub fn pad_val(&self) -> PAD_VAL_R {
655        PAD_VAL_R::new(((self.bits >> 24) & 0xff) as u8)
656    }
657}
658impl W {
659    #[doc = "Bits 0:1 - Minimum size of SDRAM block write"]
660    #[inline(always)]
661    #[must_use]
662    pub fn min_sdr_wr_size(&mut self) -> MIN_SDR_WR_SIZE_W<CSIC_DMA_CFG_SPEC> {
663        MIN_SDR_WR_SIZE_W::new(self, 0)
664    }
665    #[doc = "Bits 6:9 - Fps down sample"]
666    #[inline(always)]
667    #[must_use]
668    pub fn fps_ds(&mut self) -> FPS_DS_W<CSIC_DMA_CFG_SPEC> {
669        FPS_DS_W::new(self, 6)
670    }
671    #[doc = "Bits 10:11 - Field selection"]
672    #[inline(always)]
673    #[must_use]
674    pub fn field_sel(&mut self) -> FIELD_SEL_W<CSIC_DMA_CFG_SPEC> {
675        FIELD_SEL_W::new(self, 10)
676    }
677    #[doc = "Bit 12 - Horizontal flip enable\n\nWhen enabled, the received data will be arranged in horizontal flip."]
678    #[inline(always)]
679    #[must_use]
680    pub fn hflip_en(&mut self) -> HFLIP_EN_W<CSIC_DMA_CFG_SPEC> {
681        HFLIP_EN_W::new(self, 12)
682    }
683    #[doc = "Bit 13 - Vertical flip enable\n\nWhen enabled, the received data will be arranged in vertical flip."]
684    #[inline(always)]
685    #[must_use]
686    pub fn vflip_en(&mut self) -> VFLIP_EN_W<CSIC_DMA_CFG_SPEC> {
687        VFLIP_EN_W::new(self, 13)
688    }
689    #[doc = "Bits 16:19 - Output data format\n\nWhen the input format is set to RAW stream\n\n0000: field-raw-8\n\n0001: field-raw-10\n\n0010: field-raw-12\n\n0011: reserved\n\n0100: field-rgb565\n\n0101: field-rgb888\n\n0110: field-prgb888\n\n0111: reserved\n\n1000: frame-raw-8\n\n1001: frame-raw-10\n\n1010: frame-raw-12\n\n1011: reserved\n\n1100: frame-rgb565\n\n1101: frame-rgb888\n\n1110: frame-prgb888\n\n1111: reserved\n\nWhen the input format is set to YUV422\n\n0000: field planar YCbCr 422\n\n0001: field planar YCbCr 420\n\n0010: frame planar YCbCr 420\n\n0011: frame planar YCbCr 422\n\n0100: field planar YCbCr 422 UV combined (UV sequence)\n\n0101: field planar YCbCr 420 UV combined (UV sequence)\n\n0110: frame planar YCbCr 420 UV combined (UV sequence)\n\n0111: frame planar YCbCr 422 UV combined (UV sequence)\n\n1000: filed planar YCbCr 422 UV combined (VU sequence)\n\n1001: field planar YCbCr 420 UV combined (VU sequence)\n\n1010: frame planar YCbCr 420 UV combined (VU sequence)\n\n1011: frame planar YCbCr 422 UV combined (VU sequence)\n\n1100: reserved\n\n1101: field YCbCr 400\n\n1110: reserved\n\n1111: frame YCbCr 400\n\nWhen the input format is set to YUV420\n\n0000: reserved\n\n0001: field planar YCbCr 420\n\n0010: frame planar YCbCr 420\n\n0011: reserved\n\n0100: reserved\n\n0101: field planar YCbCr 420 UV combined (UV sequence)\n\n0110: frame planar YCbCr 420 UV combined (UV sequence) 0111~1000: reserved\n\n1001: field planar YCbCr 420 UV combined (VU sequence)\n\n1010: frame planar YCbCr 420 UV combined (VU sequence) 1011~1100: reserved\n\n1101: field YCbCr 400\n\n1110: reserved\n\n1111: frame YCbCr 400"]
690    #[inline(always)]
691    #[must_use]
692    pub fn output_fmt(&mut self) -> OUTPUT_FMT_W<CSIC_DMA_CFG_SPEC> {
693        OUTPUT_FMT_W::new(self, 16)
694    }
695    #[doc = "Bit 20 - 10-bit store configuration"]
696    #[inline(always)]
697    #[must_use]
698    pub fn yuv_10bit_store_configuration(
699        &mut self,
700    ) -> YUV_10BIT_STORE_CONFIGURATION_W<CSIC_DMA_CFG_SPEC> {
701        YUV_10BIT_STORE_CONFIGURATION_W::new(self, 20)
702    }
703    #[doc = "Bit 21 - 10-bit input cut to 8-bit"]
704    #[inline(always)]
705    #[must_use]
706    pub fn yuv_10bit_cut_8bit(&mut self) -> YUV_10BIT_CUT_8BIT_W<CSIC_DMA_CFG_SPEC> {
707        YUV_10BIT_CUT_8BIT_W::new(self, 21)
708    }
709    #[doc = "Bits 24:31 - Padding value when OUTPUT_FMT is prgb888\n\n0x00-0xff"]
710    #[inline(always)]
711    #[must_use]
712    pub fn pad_val(&mut self) -> PAD_VAL_W<CSIC_DMA_CFG_SPEC> {
713        PAD_VAL_W::new(self, 24)
714    }
715    #[doc = r" Writes raw bits to the register."]
716    #[doc = r""]
717    #[doc = r" # Safety"]
718    #[doc = r""]
719    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
720    #[inline(always)]
721    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
722        self.bits = bits;
723        self
724    }
725}
726#[doc = "CSIC DMA Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csic_dma_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csic_dma_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
727pub struct CSIC_DMA_CFG_SPEC;
728impl crate::RegisterSpec for CSIC_DMA_CFG_SPEC {
729    type Ux = u32;
730}
731#[doc = "`read()` method returns [`csic_dma_cfg::R`](R) reader structure"]
732impl crate::Readable for CSIC_DMA_CFG_SPEC {}
733#[doc = "`write(|w| ..)` method takes [`csic_dma_cfg::W`](W) writer structure"]
734impl crate::Writable for CSIC_DMA_CFG_SPEC {
735    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
736    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
737}
738#[doc = "`reset()` method sets csic_dma_cfg to value 0"]
739impl crate::Resettable for CSIC_DMA_CFG_SPEC {
740    const RESET_VALUE: Self::Ux = 0;
741}
d1_pac/csic/csic_dma/csic_dma_cfg.rs

d1_pac/csic/csic_dma/
csic_dma_cfg.rs
