d1_pac/csic/csic_dma/
csic_dma_cap_sta.rs

1#[doc = "Register `csic_dma_cap_sta` reader"]
2pub type R = crate::R<CSIC_DMA_CAP_STA_SPEC>;
3#[doc = "Register `csic_dma_cap_sta` writer"]
4pub type W = crate::W<CSIC_DMA_CAP_STA_SPEC>;
5#[doc = "Field `scap_sta` reader - Still capture in progress\n\nIndicates the CSI is capturing still image data (single frame). The bit is set at the start of the first frame after enabling still frame capture. It clears itself after the last pixel of the first frame is captured.\n\nFor CCIR656 interface, if the output format is frame planar YCbCr 420 mode, the frame end means the field2 end, the other frame end means filed end."]
6pub type SCAP_STA_R = crate::BitReader;
7#[doc = "Field `vcap_sta` reader - Video capture in progress\n\nIndicates the CSI is capturing video image data (multiple frames). The bit is set at the start of the first frame after enabling video capture. When software disables video capture, it clears itself after the last pixel of the current frame is captured."]
8pub type VCAP_STA_R = crate::BitReader;
9#[doc = "Field `field_sta` reader - The status of the received field"]
10pub type FIELD_STA_R = crate::BitReader<FIELD_STA_A>;
11#[doc = "The status of the received field\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum FIELD_STA_A {
14    #[doc = "0: Field 0"]
15    F_IELD_0 = 0,
16    #[doc = "1: Field 1"]
17    F_IELD_1 = 1,
18}
19impl From<FIELD_STA_A> for bool {
20    #[inline(always)]
21    fn from(variant: FIELD_STA_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl FIELD_STA_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> FIELD_STA_A {
29        match self.bits {
30            false => FIELD_STA_A::F_IELD_0,
31            true => FIELD_STA_A::F_IELD_1,
32        }
33    }
34    #[doc = "Field 0"]
35    #[inline(always)]
36    pub fn is_f_ield_0(&self) -> bool {
37        *self == FIELD_STA_A::F_IELD_0
38    }
39    #[doc = "Field 1"]
40    #[inline(always)]
41    pub fn is_f_ield_1(&self) -> bool {
42        *self == FIELD_STA_A::F_IELD_1
43    }
44}
45impl R {
46    #[doc = "Bit 0 - Still capture in progress\n\nIndicates the CSI is capturing still image data (single frame). The bit is set at the start of the first frame after enabling still frame capture. It clears itself after the last pixel of the first frame is captured.\n\nFor CCIR656 interface, if the output format is frame planar YCbCr 420 mode, the frame end means the field2 end, the other frame end means filed end."]
47    #[inline(always)]
48    pub fn scap_sta(&self) -> SCAP_STA_R {
49        SCAP_STA_R::new((self.bits & 1) != 0)
50    }
51    #[doc = "Bit 1 - Video capture in progress\n\nIndicates the CSI is capturing video image data (multiple frames). The bit is set at the start of the first frame after enabling video capture. When software disables video capture, it clears itself after the last pixel of the current frame is captured."]
52    #[inline(always)]
53    pub fn vcap_sta(&self) -> VCAP_STA_R {
54        VCAP_STA_R::new(((self.bits >> 1) & 1) != 0)
55    }
56    #[doc = "Bit 2 - The status of the received field"]
57    #[inline(always)]
58    pub fn field_sta(&self) -> FIELD_STA_R {
59        FIELD_STA_R::new(((self.bits >> 2) & 1) != 0)
60    }
61}
62impl W {
63    #[doc = r" Writes raw bits to the register."]
64    #[doc = r""]
65    #[doc = r" # Safety"]
66    #[doc = r""]
67    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
68    #[inline(always)]
69    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
70        self.bits = bits;
71        self
72    }
73}
74#[doc = "CSIC DMA Capture Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csic_dma_cap_sta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csic_dma_cap_sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
75pub struct CSIC_DMA_CAP_STA_SPEC;
76impl crate::RegisterSpec for CSIC_DMA_CAP_STA_SPEC {
77    type Ux = u32;
78}
79#[doc = "`read()` method returns [`csic_dma_cap_sta::R`](R) reader structure"]
80impl crate::Readable for CSIC_DMA_CAP_STA_SPEC {}
81#[doc = "`write(|w| ..)` method takes [`csic_dma_cap_sta::W`](W) writer structure"]
82impl crate::Writable for CSIC_DMA_CAP_STA_SPEC {
83    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
84    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
85}
86#[doc = "`reset()` method sets csic_dma_cap_sta to value 0"]
87impl crate::Resettable for CSIC_DMA_CAP_STA_SPEC {
88    const RESET_VALUE: Self::Ux = 0;
89}
d1_pac/csic/csic_dma/csic_dma_cap_sta.rs

d1_pac/csic/csic_dma/
csic_dma_cap_sta.rs
