d1_pac/csic/csic_dma/
csic_dma_buf_th.rs

1#[doc = "Register `csic_dma_buf_th` reader"]
2pub type R = crate::R<CSIC_DMA_BUF_TH_SPEC>;
3#[doc = "Register `csic_dma_buf_th` writer"]
4pub type W = crate::W<CSIC_DMA_BUF_TH_SPEC>;
5#[doc = "Field `csic_dma_buf_addr_fifo_threshold` reader - when content in Buffer Address FIFO less than the threshold, an interrupt is set, only used in Buffer Addr FIFO Mode."]
6pub type CSIC_DMA_BUF_ADDR_FIFO_THRESHOLD_R = crate::FieldReader;
7#[doc = "Field `csic_dma_buf_addr_fifo_threshold` writer - when content in Buffer Address FIFO less than the threshold, an interrupt is set, only used in Buffer Addr FIFO Mode."]
8pub type CSIC_DMA_BUF_ADDR_FIFO_THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `csic_dma_stored_frm_threshold` reader - when stored frame counter value reaches the threshold , counter is cleared to 0 , only used in Buffer Addr FIFO Mode."]
10pub type CSIC_DMA_STORED_FRM_THRESHOLD_R = crate::FieldReader;
11#[doc = "Field `csic_dma_stored_frm_threshold` writer - when stored frame counter value reaches the threshold , counter is cleared to 0 , only used in Buffer Addr FIFO Mode."]
12pub type CSIC_DMA_STORED_FRM_THRESHOLD_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13impl R {
14    #[doc = "Bits 0:5 - when content in Buffer Address FIFO less than the threshold, an interrupt is set, only used in Buffer Addr FIFO Mode."]
15    #[inline(always)]
16    pub fn csic_dma_buf_addr_fifo_threshold(&self) -> CSIC_DMA_BUF_ADDR_FIFO_THRESHOLD_R {
17        CSIC_DMA_BUF_ADDR_FIFO_THRESHOLD_R::new((self.bits & 0x3f) as u8)
18    }
19    #[doc = "Bits 16:21 - when stored frame counter value reaches the threshold , counter is cleared to 0 , only used in Buffer Addr FIFO Mode."]
20    #[inline(always)]
21    pub fn csic_dma_stored_frm_threshold(&self) -> CSIC_DMA_STORED_FRM_THRESHOLD_R {
22        CSIC_DMA_STORED_FRM_THRESHOLD_R::new(((self.bits >> 16) & 0x3f) as u8)
23    }
24}
25impl W {
26    #[doc = "Bits 0:5 - when content in Buffer Address FIFO less than the threshold, an interrupt is set, only used in Buffer Addr FIFO Mode."]
27    #[inline(always)]
28    #[must_use]
29    pub fn csic_dma_buf_addr_fifo_threshold(
30        &mut self,
31    ) -> CSIC_DMA_BUF_ADDR_FIFO_THRESHOLD_W<CSIC_DMA_BUF_TH_SPEC> {
32        CSIC_DMA_BUF_ADDR_FIFO_THRESHOLD_W::new(self, 0)
33    }
34    #[doc = "Bits 16:21 - when stored frame counter value reaches the threshold , counter is cleared to 0 , only used in Buffer Addr FIFO Mode."]
35    #[inline(always)]
36    #[must_use]
37    pub fn csic_dma_stored_frm_threshold(
38        &mut self,
39    ) -> CSIC_DMA_STORED_FRM_THRESHOLD_W<CSIC_DMA_BUF_TH_SPEC> {
40        CSIC_DMA_STORED_FRM_THRESHOLD_W::new(self, 16)
41    }
42    #[doc = r" Writes raw bits to the register."]
43    #[doc = r""]
44    #[doc = r" # Safety"]
45    #[doc = r""]
46    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
47    #[inline(always)]
48    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
49        self.bits = bits;
50        self
51    }
52}
53#[doc = "CSIC DMA BUF Threshold Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csic_dma_buf_th::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csic_dma_buf_th::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
54pub struct CSIC_DMA_BUF_TH_SPEC;
55impl crate::RegisterSpec for CSIC_DMA_BUF_TH_SPEC {
56    type Ux = u32;
57}
58#[doc = "`read()` method returns [`csic_dma_buf_th::R`](R) reader structure"]
59impl crate::Readable for CSIC_DMA_BUF_TH_SPEC {}
60#[doc = "`write(|w| ..)` method takes [`csic_dma_buf_th::W`](W) writer structure"]
61impl crate::Writable for CSIC_DMA_BUF_TH_SPEC {
62    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
63    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
64}
65#[doc = "`reset()` method sets csic_dma_buf_th to value 0x0020_0000"]
66impl crate::Resettable for CSIC_DMA_BUF_TH_SPEC {
67    const RESET_VALUE: Self::Ux = 0x0020_0000;
68}
d1_pac/csic/csic_dma/csic_dma_buf_th.rs

d1_pac/csic/csic_dma/
csic_dma_buf_th.rs
