d1_pac/csic/csic_dma/
csic_dma_buf_addr_fifo_entry.rs

1#[doc = "Register `csic_dma_buf_addr_fifo%s_entry` reader"]
2pub type R = crate::R<CSIC_DMA_BUF_ADDR_FIFO_ENTRY_SPEC>;
3#[doc = "Register `csic_dma_buf_addr_fifo%s_entry` writer"]
4pub type W = crate::W<CSIC_DMA_BUF_ADDR_FIFO_ENTRY_SPEC>;
5#[doc = "Field `csic_dma_buf_addr_fifo_entry` reader - FIFO Entry of Buffer Address FIFO\\[i\\] for input frames to be stored, only used in Buffer Addr FIFO Mode"]
6pub type CSIC_DMA_BUF_ADDR_FIFO_ENTRY_R = crate::FieldReader<u32>;
7#[doc = "Field `csic_dma_buf_addr_fifo_entry` writer - FIFO Entry of Buffer Address FIFO\\[i\\] for input frames to be stored, only used in Buffer Addr FIFO Mode"]
8pub type CSIC_DMA_BUF_ADDR_FIFO_ENTRY_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31 - FIFO Entry of Buffer Address FIFO\\[i\\] for input frames to be stored, only used in Buffer Addr FIFO Mode"]
11    #[inline(always)]
12    pub fn csic_dma_buf_addr_fifo_entry(&self) -> CSIC_DMA_BUF_ADDR_FIFO_ENTRY_R {
13        CSIC_DMA_BUF_ADDR_FIFO_ENTRY_R::new(self.bits)
14    }
15}
16impl W {
17    #[doc = "Bits 0:31 - FIFO Entry of Buffer Address FIFO\\[i\\] for input frames to be stored, only used in Buffer Addr FIFO Mode"]
18    #[inline(always)]
19    #[must_use]
20    pub fn csic_dma_buf_addr_fifo_entry(
21        &mut self,
22    ) -> CSIC_DMA_BUF_ADDR_FIFO_ENTRY_W<CSIC_DMA_BUF_ADDR_FIFO_ENTRY_SPEC> {
23        CSIC_DMA_BUF_ADDR_FIFO_ENTRY_W::new(self, 0)
24    }
25    #[doc = r" Writes raw bits to the register."]
26    #[doc = r""]
27    #[doc = r" # Safety"]
28    #[doc = r""]
29    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
30    #[inline(always)]
31    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
32        self.bits = bits;
33        self
34    }
35}
36#[doc = "CSIC DMA BUF Address FIFO\\[i\\] Entry Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csic_dma_buf_addr_fifo_entry::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csic_dma_buf_addr_fifo_entry::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
37pub struct CSIC_DMA_BUF_ADDR_FIFO_ENTRY_SPEC;
38impl crate::RegisterSpec for CSIC_DMA_BUF_ADDR_FIFO_ENTRY_SPEC {
39    type Ux = u32;
40}
41#[doc = "`read()` method returns [`csic_dma_buf_addr_fifo_entry::R`](R) reader structure"]
42impl crate::Readable for CSIC_DMA_BUF_ADDR_FIFO_ENTRY_SPEC {}
43#[doc = "`write(|w| ..)` method takes [`csic_dma_buf_addr_fifo_entry::W`](W) writer structure"]
44impl crate::Writable for CSIC_DMA_BUF_ADDR_FIFO_ENTRY_SPEC {
45    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
46    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
47}
48#[doc = "`reset()` method sets csic_dma_buf_addr_fifo%s_entry to value 0"]
49impl crate::Resettable for CSIC_DMA_BUF_ADDR_FIFO_ENTRY_SPEC {
50    const RESET_VALUE: Self::Ux = 0;
51}
d1_pac/csic/csic_dma/csic_dma_buf_addr_fifo_entry.rs

d1_pac/csic/csic_dma/
csic_dma_buf_addr_fifo_entry.rs
