d1_pac/csic/csic_ccu/
ccu_post0_clk_en.rs

1#[doc = "Register `ccu_post0_clk_en` reader"]
2pub type R = crate::R<CCU_POST0_CLK_EN_SPEC>;
3#[doc = "Register `ccu_post0_clk_en` writer"]
4pub type W = crate::W<CCU_POST0_CLK_EN_SPEC>;
5#[doc = "Field `mcsi_bk_clk_enable[0-1]` reader - "]
6pub type MCSI_BK_CLK_ENABLE_R = crate::BitReader<MCSI_BK_CLK_ENABLE_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum MCSI_BK_CLK_ENABLE_A {
10    #[doc = "0: BK\\[i\\] clock disable"]
11    DISABLE = 0,
12    #[doc = "1: BK\\[i\\] clock enable,when MCSI_POST0_CLK_ENABLE is 1"]
13    ENABLE = 1,
14}
15impl From<MCSI_BK_CLK_ENABLE_A> for bool {
16    #[inline(always)]
17    fn from(variant: MCSI_BK_CLK_ENABLE_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl MCSI_BK_CLK_ENABLE_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> MCSI_BK_CLK_ENABLE_A {
25        match self.bits {
26            false => MCSI_BK_CLK_ENABLE_A::DISABLE,
27            true => MCSI_BK_CLK_ENABLE_A::ENABLE,
28        }
29    }
30    #[doc = "BK\\[i\\] clock disable"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == MCSI_BK_CLK_ENABLE_A::DISABLE
34    }
35    #[doc = "BK\\[i\\] clock enable,when MCSI_POST0_CLK_ENABLE is 1"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == MCSI_BK_CLK_ENABLE_A::ENABLE
39    }
40}
41#[doc = "Field `mcsi_bk_clk_enable[0-1]` writer - "]
42pub type MCSI_BK_CLK_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, MCSI_BK_CLK_ENABLE_A>;
43impl<'a, REG> MCSI_BK_CLK_ENABLE_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "BK\\[i\\] clock disable"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(MCSI_BK_CLK_ENABLE_A::DISABLE)
51    }
52    #[doc = "BK\\[i\\] clock enable,when MCSI_POST0_CLK_ENABLE is 1"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(MCSI_BK_CLK_ENABLE_A::ENABLE)
56    }
57}
58#[doc = "Field `mcsi_post0_clk_enable` reader - "]
59pub type MCSI_POST0_CLK_ENABLE_R = crate::BitReader<MCSI_POST0_CLK_ENABLE_A>;
60#[doc = "\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum MCSI_POST0_CLK_ENABLE_A {
63    #[doc = "0: POST0 clock disable"]
64    DISABLE = 0,
65    #[doc = "1: POST0 clock enable"]
66    ENABLE = 1,
67}
68impl From<MCSI_POST0_CLK_ENABLE_A> for bool {
69    #[inline(always)]
70    fn from(variant: MCSI_POST0_CLK_ENABLE_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl MCSI_POST0_CLK_ENABLE_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> MCSI_POST0_CLK_ENABLE_A {
78        match self.bits {
79            false => MCSI_POST0_CLK_ENABLE_A::DISABLE,
80            true => MCSI_POST0_CLK_ENABLE_A::ENABLE,
81        }
82    }
83    #[doc = "POST0 clock disable"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == MCSI_POST0_CLK_ENABLE_A::DISABLE
87    }
88    #[doc = "POST0 clock enable"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == MCSI_POST0_CLK_ENABLE_A::ENABLE
92    }
93}
94#[doc = "Field `mcsi_post0_clk_enable` writer - "]
95pub type MCSI_POST0_CLK_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, MCSI_POST0_CLK_ENABLE_A>;
96impl<'a, REG> MCSI_POST0_CLK_ENABLE_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "POST0 clock disable"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(MCSI_POST0_CLK_ENABLE_A::DISABLE)
104    }
105    #[doc = "POST0 clock enable"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(MCSI_POST0_CLK_ENABLE_A::ENABLE)
109    }
110}
111impl R {
112    #[doc = "\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `mcsi_bk0_clk_enable` field"]
113    #[inline(always)]
114    pub fn mcsi_bk_clk_enable(&self, n: u8) -> MCSI_BK_CLK_ENABLE_R {
115        #[allow(clippy::no_effect)]
116        [(); 2][n as usize];
117        MCSI_BK_CLK_ENABLE_R::new(((self.bits >> n) & 1) != 0)
118    }
119    #[doc = "Bit 0 - mcsi_bk0_clk_enable"]
120    #[inline(always)]
121    pub fn mcsi_bk0_clk_enable(&self) -> MCSI_BK_CLK_ENABLE_R {
122        MCSI_BK_CLK_ENABLE_R::new((self.bits & 1) != 0)
123    }
124    #[doc = "Bit 1 - mcsi_bk1_clk_enable"]
125    #[inline(always)]
126    pub fn mcsi_bk1_clk_enable(&self) -> MCSI_BK_CLK_ENABLE_R {
127        MCSI_BK_CLK_ENABLE_R::new(((self.bits >> 1) & 1) != 0)
128    }
129    #[doc = "Bit 16"]
130    #[inline(always)]
131    pub fn mcsi_post0_clk_enable(&self) -> MCSI_POST0_CLK_ENABLE_R {
132        MCSI_POST0_CLK_ENABLE_R::new(((self.bits >> 16) & 1) != 0)
133    }
134}
135impl W {
136    #[doc = "\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `mcsi_bk0_clk_enable` field"]
137    #[inline(always)]
138    #[must_use]
139    pub fn mcsi_bk_clk_enable(&mut self, n: u8) -> MCSI_BK_CLK_ENABLE_W<CCU_POST0_CLK_EN_SPEC> {
140        #[allow(clippy::no_effect)]
141        [(); 2][n as usize];
142        MCSI_BK_CLK_ENABLE_W::new(self, n)
143    }
144    #[doc = "Bit 0 - mcsi_bk0_clk_enable"]
145    #[inline(always)]
146    #[must_use]
147    pub fn mcsi_bk0_clk_enable(&mut self) -> MCSI_BK_CLK_ENABLE_W<CCU_POST0_CLK_EN_SPEC> {
148        MCSI_BK_CLK_ENABLE_W::new(self, 0)
149    }
150    #[doc = "Bit 1 - mcsi_bk1_clk_enable"]
151    #[inline(always)]
152    #[must_use]
153    pub fn mcsi_bk1_clk_enable(&mut self) -> MCSI_BK_CLK_ENABLE_W<CCU_POST0_CLK_EN_SPEC> {
154        MCSI_BK_CLK_ENABLE_W::new(self, 1)
155    }
156    #[doc = "Bit 16"]
157    #[inline(always)]
158    #[must_use]
159    pub fn mcsi_post0_clk_enable(&mut self) -> MCSI_POST0_CLK_ENABLE_W<CCU_POST0_CLK_EN_SPEC> {
160        MCSI_POST0_CLK_ENABLE_W::new(self, 16)
161    }
162    #[doc = r" Writes raw bits to the register."]
163    #[doc = r""]
164    #[doc = r" # Safety"]
165    #[doc = r""]
166    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
167    #[inline(always)]
168    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
169        self.bits = bits;
170        self
171    }
172}
173#[doc = "CCU Post0 Clock Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccu_post0_clk_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccu_post0_clk_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
174pub struct CCU_POST0_CLK_EN_SPEC;
175impl crate::RegisterSpec for CCU_POST0_CLK_EN_SPEC {
176    type Ux = u32;
177}
178#[doc = "`read()` method returns [`ccu_post0_clk_en::R`](R) reader structure"]
179impl crate::Readable for CCU_POST0_CLK_EN_SPEC {}
180#[doc = "`write(|w| ..)` method takes [`ccu_post0_clk_en::W`](W) writer structure"]
181impl crate::Writable for CCU_POST0_CLK_EN_SPEC {
182    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
183    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
184}
185#[doc = "`reset()` method sets ccu_post0_clk_en to value 0"]
186impl crate::Resettable for CCU_POST0_CLK_EN_SPEC {
187    const RESET_VALUE: Self::Ux = 0;
188}
d1_pac/csic/csic_ccu/ccu_post0_clk_en.rs

d1_pac/csic/csic_ccu/
ccu_post0_clk_en.rs
