d1_pac/csic/csic_ccu/
ccu_clk_mode.rs

1#[doc = "Register `ccu_clk_mode` reader"]
2pub type R = crate::R<CCU_CLK_MODE_SPEC>;
3#[doc = "Register `ccu_clk_mode` writer"]
4pub type W = crate::W<CCU_CLK_MODE_SPEC>;
5#[doc = "Field `ccu_clk_gating_disable` reader - "]
6pub type CCU_CLK_GATING_DISABLE_R = crate::BitReader<CCU_CLK_GATING_DISABLE_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum CCU_CLK_GATING_DISABLE_A {
10    #[doc = "0: CCU Clock Gating Registers(0x0004~0x0010) effect"]
11    EFFECT = 0,
12    #[doc = "1: CCU Clock Gating Registers(0x0004~0x0010) not effect"]
13    NOT_EFFECT = 1,
14}
15impl From<CCU_CLK_GATING_DISABLE_A> for bool {
16    #[inline(always)]
17    fn from(variant: CCU_CLK_GATING_DISABLE_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl CCU_CLK_GATING_DISABLE_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> CCU_CLK_GATING_DISABLE_A {
25        match self.bits {
26            false => CCU_CLK_GATING_DISABLE_A::EFFECT,
27            true => CCU_CLK_GATING_DISABLE_A::NOT_EFFECT,
28        }
29    }
30    #[doc = "CCU Clock Gating Registers(0x0004~0x0010) effect"]
31    #[inline(always)]
32    pub fn is_effect(&self) -> bool {
33        *self == CCU_CLK_GATING_DISABLE_A::EFFECT
34    }
35    #[doc = "CCU Clock Gating Registers(0x0004~0x0010) not effect"]
36    #[inline(always)]
37    pub fn is_not_effect(&self) -> bool {
38        *self == CCU_CLK_GATING_DISABLE_A::NOT_EFFECT
39    }
40}
41#[doc = "Field `ccu_clk_gating_disable` writer - "]
42pub type CCU_CLK_GATING_DISABLE_W<'a, REG> = crate::BitWriter<'a, REG, CCU_CLK_GATING_DISABLE_A>;
43impl<'a, REG> CCU_CLK_GATING_DISABLE_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "CCU Clock Gating Registers(0x0004~0x0010) effect"]
48    #[inline(always)]
49    pub fn effect(self) -> &'a mut crate::W<REG> {
50        self.variant(CCU_CLK_GATING_DISABLE_A::EFFECT)
51    }
52    #[doc = "CCU Clock Gating Registers(0x0004~0x0010) not effect"]
53    #[inline(always)]
54    pub fn not_effect(self) -> &'a mut crate::W<REG> {
55        self.variant(CCU_CLK_GATING_DISABLE_A::NOT_EFFECT)
56    }
57}
58impl R {
59    #[doc = "Bit 31"]
60    #[inline(always)]
61    pub fn ccu_clk_gating_disable(&self) -> CCU_CLK_GATING_DISABLE_R {
62        CCU_CLK_GATING_DISABLE_R::new(((self.bits >> 31) & 1) != 0)
63    }
64}
65impl W {
66    #[doc = "Bit 31"]
67    #[inline(always)]
68    #[must_use]
69    pub fn ccu_clk_gating_disable(&mut self) -> CCU_CLK_GATING_DISABLE_W<CCU_CLK_MODE_SPEC> {
70        CCU_CLK_GATING_DISABLE_W::new(self, 31)
71    }
72    #[doc = r" Writes raw bits to the register."]
73    #[doc = r""]
74    #[doc = r" # Safety"]
75    #[doc = r""]
76    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
77    #[inline(always)]
78    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
79        self.bits = bits;
80        self
81    }
82}
83#[doc = "CCU Clock Mode Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccu_clk_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccu_clk_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
84pub struct CCU_CLK_MODE_SPEC;
85impl crate::RegisterSpec for CCU_CLK_MODE_SPEC {
86    type Ux = u32;
87}
88#[doc = "`read()` method returns [`ccu_clk_mode::R`](R) reader structure"]
89impl crate::Readable for CCU_CLK_MODE_SPEC {}
90#[doc = "`write(|w| ..)` method takes [`ccu_clk_mode::W`](W) writer structure"]
91impl crate::Writable for CCU_CLK_MODE_SPEC {
92    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
93    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
94}
95#[doc = "`reset()` method sets ccu_clk_mode to value 0"]
96impl crate::Resettable for CCU_CLK_MODE_SPEC {
97    const RESET_VALUE: Self::Ux = 0;
98}
d1_pac/csic/csic_ccu/ccu_clk_mode.rs

d1_pac/csic/csic_ccu/
ccu_clk_mode.rs
