d1_pac/cir_tx/
cir_txint.rs

1#[doc = "Register `cir_txint` reader"]
2pub type R = crate::R<CIR_TXINT_SPEC>;
3#[doc = "Register `cir_txint` writer"]
4pub type W = crate::W<CIR_TXINT_SPEC>;
5#[doc = "Field `tpei_tui_en` reader - Transmit Packet End Interrupt Enable for Cyclical Pulse / Transmitter FIFO Underrun Interrupt Enable for Non-cyclical Pulse"]
6pub type TPEI_TUI_EN_R = crate::BitReader<TPEI_TUI_EN_A>;
7#[doc = "Transmit Packet End Interrupt Enable for Cyclical Pulse / Transmitter FIFO Underrun Interrupt Enable for Non-cyclical Pulse\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TPEI_TUI_EN_A {
10    #[doc = "0: Disable"]
11    DISABLE = 0,
12    #[doc = "1: Enable"]
13    ENABLE = 1,
14}
15impl From<TPEI_TUI_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: TPEI_TUI_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl TPEI_TUI_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> TPEI_TUI_EN_A {
25        match self.bits {
26            false => TPEI_TUI_EN_A::DISABLE,
27            true => TPEI_TUI_EN_A::ENABLE,
28        }
29    }
30    #[doc = "Disable"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == TPEI_TUI_EN_A::DISABLE
34    }
35    #[doc = "Enable"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == TPEI_TUI_EN_A::ENABLE
39    }
40}
41#[doc = "Field `tpei_tui_en` writer - Transmit Packet End Interrupt Enable for Cyclical Pulse / Transmitter FIFO Underrun Interrupt Enable for Non-cyclical Pulse"]
42pub type TPEI_TUI_EN_W<'a, REG> = crate::BitWriter<'a, REG, TPEI_TUI_EN_A>;
43impl<'a, REG> TPEI_TUI_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(TPEI_TUI_EN_A::DISABLE)
51    }
52    #[doc = "Enable"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(TPEI_TUI_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `tai_en` reader - TX FIFO Available Interrupt Enable"]
59pub type TAI_EN_R = crate::BitReader<TAI_EN_A>;
60#[doc = "TX FIFO Available Interrupt Enable\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum TAI_EN_A {
63    #[doc = "0: Disable"]
64    DISABLE = 0,
65    #[doc = "1: Enable"]
66    ENABLE = 1,
67}
68impl From<TAI_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: TAI_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl TAI_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> TAI_EN_A {
78        match self.bits {
79            false => TAI_EN_A::DISABLE,
80            true => TAI_EN_A::ENABLE,
81        }
82    }
83    #[doc = "Disable"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == TAI_EN_A::DISABLE
87    }
88    #[doc = "Enable"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == TAI_EN_A::ENABLE
92    }
93}
94#[doc = "Field `tai_en` writer - TX FIFO Available Interrupt Enable"]
95pub type TAI_EN_W<'a, REG> = crate::BitWriter<'a, REG, TAI_EN_A>;
96impl<'a, REG> TAI_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Disable"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(TAI_EN_A::DISABLE)
104    }
105    #[doc = "Enable"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(TAI_EN_A::ENABLE)
109    }
110}
111#[doc = "Field `drq_en` reader - TX FIFO DMA Enable\n\nWhen it is set to '1', the TX FIFO DRQ is asserted if the number of the transmitting data in the FIFO is less than the RAL. The DRQ is de-asserted when the condition fails."]
112pub type DRQ_EN_R = crate::BitReader<DRQ_EN_A>;
113#[doc = "TX FIFO DMA Enable\n\nWhen it is set to '1', the TX FIFO DRQ is asserted if the number of the transmitting data in the FIFO is less than the RAL. The DRQ is de-asserted when the condition fails.\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum DRQ_EN_A {
116    #[doc = "0: Disable"]
117    DISABLE = 0,
118    #[doc = "1: Enable"]
119    ENABLE = 1,
120}
121impl From<DRQ_EN_A> for bool {
122    #[inline(always)]
123    fn from(variant: DRQ_EN_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl DRQ_EN_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> DRQ_EN_A {
131        match self.bits {
132            false => DRQ_EN_A::DISABLE,
133            true => DRQ_EN_A::ENABLE,
134        }
135    }
136    #[doc = "Disable"]
137    #[inline(always)]
138    pub fn is_disable(&self) -> bool {
139        *self == DRQ_EN_A::DISABLE
140    }
141    #[doc = "Enable"]
142    #[inline(always)]
143    pub fn is_enable(&self) -> bool {
144        *self == DRQ_EN_A::ENABLE
145    }
146}
147#[doc = "Field `drq_en` writer - TX FIFO DMA Enable\n\nWhen it is set to '1', the TX FIFO DRQ is asserted if the number of the transmitting data in the FIFO is less than the RAL. The DRQ is de-asserted when the condition fails."]
148pub type DRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, DRQ_EN_A>;
149impl<'a, REG> DRQ_EN_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Disable"]
154    #[inline(always)]
155    pub fn disable(self) -> &'a mut crate::W<REG> {
156        self.variant(DRQ_EN_A::DISABLE)
157    }
158    #[doc = "Enable"]
159    #[inline(always)]
160    pub fn enable(self) -> &'a mut crate::W<REG> {
161        self.variant(DRQ_EN_A::ENABLE)
162    }
163}
164impl R {
165    #[doc = "Bit 0 - Transmit Packet End Interrupt Enable for Cyclical Pulse / Transmitter FIFO Underrun Interrupt Enable for Non-cyclical Pulse"]
166    #[inline(always)]
167    pub fn tpei_tui_en(&self) -> TPEI_TUI_EN_R {
168        TPEI_TUI_EN_R::new((self.bits & 1) != 0)
169    }
170    #[doc = "Bit 1 - TX FIFO Available Interrupt Enable"]
171    #[inline(always)]
172    pub fn tai_en(&self) -> TAI_EN_R {
173        TAI_EN_R::new(((self.bits >> 1) & 1) != 0)
174    }
175    #[doc = "Bit 2 - TX FIFO DMA Enable\n\nWhen it is set to '1', the TX FIFO DRQ is asserted if the number of the transmitting data in the FIFO is less than the RAL. The DRQ is de-asserted when the condition fails."]
176    #[inline(always)]
177    pub fn drq_en(&self) -> DRQ_EN_R {
178        DRQ_EN_R::new(((self.bits >> 2) & 1) != 0)
179    }
180}
181impl W {
182    #[doc = "Bit 0 - Transmit Packet End Interrupt Enable for Cyclical Pulse / Transmitter FIFO Underrun Interrupt Enable for Non-cyclical Pulse"]
183    #[inline(always)]
184    #[must_use]
185    pub fn tpei_tui_en(&mut self) -> TPEI_TUI_EN_W<CIR_TXINT_SPEC> {
186        TPEI_TUI_EN_W::new(self, 0)
187    }
188    #[doc = "Bit 1 - TX FIFO Available Interrupt Enable"]
189    #[inline(always)]
190    #[must_use]
191    pub fn tai_en(&mut self) -> TAI_EN_W<CIR_TXINT_SPEC> {
192        TAI_EN_W::new(self, 1)
193    }
194    #[doc = "Bit 2 - TX FIFO DMA Enable\n\nWhen it is set to '1', the TX FIFO DRQ is asserted if the number of the transmitting data in the FIFO is less than the RAL. The DRQ is de-asserted when the condition fails."]
195    #[inline(always)]
196    #[must_use]
197    pub fn drq_en(&mut self) -> DRQ_EN_W<CIR_TXINT_SPEC> {
198        DRQ_EN_W::new(self, 2)
199    }
200    #[doc = r" Writes raw bits to the register."]
201    #[doc = r""]
202    #[doc = r" # Safety"]
203    #[doc = r""]
204    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
205    #[inline(always)]
206    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
207        self.bits = bits;
208        self
209    }
210}
211#[doc = "CIR Transmit Interrupt Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_txint::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_txint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
212pub struct CIR_TXINT_SPEC;
213impl crate::RegisterSpec for CIR_TXINT_SPEC {
214    type Ux = u32;
215}
216#[doc = "`read()` method returns [`cir_txint::R`](R) reader structure"]
217impl crate::Readable for CIR_TXINT_SPEC {}
218#[doc = "`write(|w| ..)` method takes [`cir_txint::W`](W) writer structure"]
219impl crate::Writable for CIR_TXINT_SPEC {
220    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
221    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
222}
223#[doc = "`reset()` method sets cir_txint to value 0"]
224impl crate::Resettable for CIR_TXINT_SPEC {
225    const RESET_VALUE: Self::Ux = 0;
226}
d1_pac/cir_tx/cir_txint.rs

d1_pac/cir_tx/
cir_txint.rs
