d1_pac/cir_tx/
cir_txfifo.rs

1#[doc = "Register `cir_txfifo` reader"]
2pub type R = crate::R<CIR_TXFIFO_SPEC>;
3#[doc = "Register `cir_txfifo` writer"]
4pub type W = crate::W<CIR_TXFIFO_SPEC>;
5#[doc = "Field `tbf` writer - Transmit Byte FIFO\n\nWhen the transmission is triggered, the data in the FIFO will be transmitted until the data number is transmitted completely."]
6pub type TBF_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
7impl W {
8    #[doc = "Bits 0:7 - Transmit Byte FIFO\n\nWhen the transmission is triggered, the data in the FIFO will be transmitted until the data number is transmitted completely."]
9    #[inline(always)]
10    #[must_use]
11    pub fn tbf(&mut self) -> TBF_W<CIR_TXFIFO_SPEC> {
12        TBF_W::new(self, 0)
13    }
14    #[doc = r" Writes raw bits to the register."]
15    #[doc = r""]
16    #[doc = r" # Safety"]
17    #[doc = r""]
18    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
19    #[inline(always)]
20    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
21        self.bits = bits;
22        self
23    }
24}
25#[doc = "CIR Transmit FIFO Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_txfifo::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_txfifo::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26pub struct CIR_TXFIFO_SPEC;
27impl crate::RegisterSpec for CIR_TXFIFO_SPEC {
28    type Ux = u32;
29}
30#[doc = "`read()` method returns [`cir_txfifo::R`](R) reader structure"]
31impl crate::Readable for CIR_TXFIFO_SPEC {}
32#[doc = "`write(|w| ..)` method takes [`cir_txfifo::W`](W) writer structure"]
33impl crate::Writable for CIR_TXFIFO_SPEC {
34    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
35    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
36}
37#[doc = "`reset()` method sets cir_txfifo to value 0"]
38impl crate::Resettable for CIR_TXFIFO_SPEC {
39    const RESET_VALUE: Self::Ux = 0;
40}
d1_pac/cir_tx/cir_txfifo.rs

d1_pac/cir_tx/
cir_txfifo.rs
