d1_pac/cir_tx/
cir_tmcr.rs

1#[doc = "Register `cir_tmcr` reader"]
2pub type R = crate::R<CIR_TMCR_SPEC>;
3#[doc = "Register `cir_tmcr` writer"]
4pub type W = crate::W<CIR_TMCR_SPEC>;
5#[doc = "Field `rfmc` reader - Reference Frequency of modulated carrier.\n\nReference Frequency of modulated carrier based on a division of a fixed functional clock (FCLK). The range of the modulated carrier is usually 30 kHz to 60 kHz. Most consumer electronics is 38 kHz.\n\nThe default modulated carrier is 38 kHz when FCLK is 12 MHz.\n\nRFMC= FCLK/((N+1)*(DRMC+2))."]
6pub type RFMC_R = crate::FieldReader;
7#[doc = "Field `rfmc` writer - Reference Frequency of modulated carrier.\n\nReference Frequency of modulated carrier based on a division of a fixed functional clock (FCLK). The range of the modulated carrier is usually 30 kHz to 60 kHz. Most consumer electronics is 38 kHz.\n\nThe default modulated carrier is 38 kHz when FCLK is 12 MHz.\n\nRFMC= FCLK/((N+1)*(DRMC+2))."]
8pub type RFMC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9impl R {
10    #[doc = "Bits 0:7 - Reference Frequency of modulated carrier.\n\nReference Frequency of modulated carrier based on a division of a fixed functional clock (FCLK). The range of the modulated carrier is usually 30 kHz to 60 kHz. Most consumer electronics is 38 kHz.\n\nThe default modulated carrier is 38 kHz when FCLK is 12 MHz.\n\nRFMC= FCLK/((N+1)*(DRMC+2))."]
11    #[inline(always)]
12    pub fn rfmc(&self) -> RFMC_R {
13        RFMC_R::new((self.bits & 0xff) as u8)
14    }
15}
16impl W {
17    #[doc = "Bits 0:7 - Reference Frequency of modulated carrier.\n\nReference Frequency of modulated carrier based on a division of a fixed functional clock (FCLK). The range of the modulated carrier is usually 30 kHz to 60 kHz. Most consumer electronics is 38 kHz.\n\nThe default modulated carrier is 38 kHz when FCLK is 12 MHz.\n\nRFMC= FCLK/((N+1)*(DRMC+2))."]
18    #[inline(always)]
19    #[must_use]
20    pub fn rfmc(&mut self) -> RFMC_W<CIR_TMCR_SPEC> {
21        RFMC_W::new(self, 0)
22    }
23    #[doc = r" Writes raw bits to the register."]
24    #[doc = r""]
25    #[doc = r" # Safety"]
26    #[doc = r""]
27    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
28    #[inline(always)]
29    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
30        self.bits = bits;
31        self
32    }
33}
34#[doc = "CIR Transmit Modulation Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_tmcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_tmcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
35pub struct CIR_TMCR_SPEC;
36impl crate::RegisterSpec for CIR_TMCR_SPEC {
37    type Ux = u32;
38}
39#[doc = "`read()` method returns [`cir_tmcr::R`](R) reader structure"]
40impl crate::Readable for CIR_TMCR_SPEC {}
41#[doc = "`write(|w| ..)` method takes [`cir_tmcr::W`](W) writer structure"]
42impl crate::Writable for CIR_TMCR_SPEC {
43    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
44    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
45}
46#[doc = "`reset()` method sets cir_tmcr to value 0x9e"]
47impl crate::Resettable for CIR_TMCR_SPEC {
48    const RESET_VALUE: Self::Ux = 0x9e;
49}
d1_pac/cir_tx/cir_tmcr.rs

d1_pac/cir_tx/
cir_tmcr.rs
