d1_pac/cir_tx/
cir_tglr.rs

1#[doc = "Register `cir_tglr` reader"]
2pub type R = crate::R<CIR_TGLR_SPEC>;
3#[doc = "Register `cir_tglr` writer"]
4pub type W = crate::W<CIR_TGLR_SPEC>;
5#[doc = "Field `txen` reader - Transmit Block Enable"]
6pub type TXEN_R = crate::BitReader<TXEN_A>;
7#[doc = "Transmit Block Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TXEN_A {
10    #[doc = "0: Disable the CIR Transmitter"]
11    DISABLE = 0,
12    #[doc = "1: Enable the CIR Transmitter"]
13    ENABLE = 1,
14}
15impl From<TXEN_A> for bool {
16    #[inline(always)]
17    fn from(variant: TXEN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl TXEN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> TXEN_A {
25        match self.bits {
26            false => TXEN_A::DISABLE,
27            true => TXEN_A::ENABLE,
28        }
29    }
30    #[doc = "Disable the CIR Transmitter"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == TXEN_A::DISABLE
34    }
35    #[doc = "Enable the CIR Transmitter"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == TXEN_A::ENABLE
39    }
40}
41#[doc = "Field `txen` writer - Transmit Block Enable"]
42pub type TXEN_W<'a, REG> = crate::BitWriter<'a, REG, TXEN_A>;
43impl<'a, REG> TXEN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable the CIR Transmitter"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(TXEN_A::DISABLE)
51    }
52    #[doc = "Enable the CIR Transmitter"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(TXEN_A::ENABLE)
56    }
57}
58#[doc = "Field `tr` reader - Transmit Reset\n\nWhen this bit is set, the transmitting is reset. The FIFO will be flushed, the TIC filed and the CSS field will be cleared during Transmit Reset. This field will automatically be cleared when the Transmit Reset is finished, and the CIR transmitter will state Idle."]
59pub type TR_R = crate::BitReader;
60#[doc = "Field `tr` writer - Transmit Reset\n\nWhen this bit is set, the transmitting is reset. The FIFO will be flushed, the TIC filed and the CSS field will be cleared during Transmit Reset. This field will automatically be cleared when the Transmit Reset is finished, and the CIR transmitter will state Idle."]
61pub type TR_W<'a, REG> = crate::BitWriter<'a, REG>;
62#[doc = "Field `tppi` reader - Transmit Pulse Polarity Invert"]
63pub type TPPI_R = crate::BitReader<TPPI_A>;
64#[doc = "Transmit Pulse Polarity Invert\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum TPPI_A {
67    #[doc = "0: Not invert transmit pulse"]
68    NOT_INVERT = 0,
69    #[doc = "1: Invert transmit pulse"]
70    INVERT = 1,
71}
72impl From<TPPI_A> for bool {
73    #[inline(always)]
74    fn from(variant: TPPI_A) -> Self {
75        variant as u8 != 0
76    }
77}
78impl TPPI_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub const fn variant(&self) -> TPPI_A {
82        match self.bits {
83            false => TPPI_A::NOT_INVERT,
84            true => TPPI_A::INVERT,
85        }
86    }
87    #[doc = "Not invert transmit pulse"]
88    #[inline(always)]
89    pub fn is_not_invert(&self) -> bool {
90        *self == TPPI_A::NOT_INVERT
91    }
92    #[doc = "Invert transmit pulse"]
93    #[inline(always)]
94    pub fn is_invert(&self) -> bool {
95        *self == TPPI_A::INVERT
96    }
97}
98#[doc = "Field `tppi` writer - Transmit Pulse Polarity Invert"]
99pub type TPPI_W<'a, REG> = crate::BitWriter<'a, REG, TPPI_A>;
100impl<'a, REG> TPPI_W<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103{
104    #[doc = "Not invert transmit pulse"]
105    #[inline(always)]
106    pub fn not_invert(self) -> &'a mut crate::W<REG> {
107        self.variant(TPPI_A::NOT_INVERT)
108    }
109    #[doc = "Invert transmit pulse"]
110    #[inline(always)]
111    pub fn invert(self) -> &'a mut crate::W<REG> {
112        self.variant(TPPI_A::INVERT)
113    }
114}
115#[doc = "Field `drmc` reader - Duty ratio of modulated carrier is high level/low level."]
116pub type DRMC_R = crate::FieldReader<DRMC_A>;
117#[doc = "Duty ratio of modulated carrier is high level/low level.\n\nValue on reset: 0"]
118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
119#[repr(u8)]
120pub enum DRMC_A {
121    #[doc = "0: Low level is equal to high level"]
122    EQUAL = 0,
123    #[doc = "1: Low level is the double of high level"]
124    DOUBLE = 1,
125    #[doc = "2: Low level is the triple of high level"]
126    TRIPLE = 2,
127}
128impl From<DRMC_A> for u8 {
129    #[inline(always)]
130    fn from(variant: DRMC_A) -> Self {
131        variant as _
132    }
133}
134impl crate::FieldSpec for DRMC_A {
135    type Ux = u8;
136}
137impl DRMC_R {
138    #[doc = "Get enumerated values variant"]
139    #[inline(always)]
140    pub const fn variant(&self) -> Option<DRMC_A> {
141        match self.bits {
142            0 => Some(DRMC_A::EQUAL),
143            1 => Some(DRMC_A::DOUBLE),
144            2 => Some(DRMC_A::TRIPLE),
145            _ => None,
146        }
147    }
148    #[doc = "Low level is equal to high level"]
149    #[inline(always)]
150    pub fn is_equal(&self) -> bool {
151        *self == DRMC_A::EQUAL
152    }
153    #[doc = "Low level is the double of high level"]
154    #[inline(always)]
155    pub fn is_double(&self) -> bool {
156        *self == DRMC_A::DOUBLE
157    }
158    #[doc = "Low level is the triple of high level"]
159    #[inline(always)]
160    pub fn is_triple(&self) -> bool {
161        *self == DRMC_A::TRIPLE
162    }
163}
164#[doc = "Field `drmc` writer - Duty ratio of modulated carrier is high level/low level."]
165pub type DRMC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DRMC_A>;
166impl<'a, REG> DRMC_W<'a, REG>
167where
168    REG: crate::Writable + crate::RegisterSpec,
169    REG::Ux: From<u8>,
170{
171    #[doc = "Low level is equal to high level"]
172    #[inline(always)]
173    pub fn equal(self) -> &'a mut crate::W<REG> {
174        self.variant(DRMC_A::EQUAL)
175    }
176    #[doc = "Low level is the double of high level"]
177    #[inline(always)]
178    pub fn double(self) -> &'a mut crate::W<REG> {
179        self.variant(DRMC_A::DOUBLE)
180    }
181    #[doc = "Low level is the triple of high level"]
182    #[inline(always)]
183    pub fn triple(self) -> &'a mut crate::W<REG> {
184        self.variant(DRMC_A::TRIPLE)
185    }
186}
187#[doc = "Field `ims` reader - Internal Modulation Select"]
188pub type IMS_R = crate::BitReader<IMS_A>;
189#[doc = "Internal Modulation Select\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum IMS_A {
192    #[doc = "0: The transmitting signal is not modulated"]
193    NOT_MODULATED = 0,
194    #[doc = "1: The transmitting signal is modulated internally"]
195    MODULATED = 1,
196}
197impl From<IMS_A> for bool {
198    #[inline(always)]
199    fn from(variant: IMS_A) -> Self {
200        variant as u8 != 0
201    }
202}
203impl IMS_R {
204    #[doc = "Get enumerated values variant"]
205    #[inline(always)]
206    pub const fn variant(&self) -> IMS_A {
207        match self.bits {
208            false => IMS_A::NOT_MODULATED,
209            true => IMS_A::MODULATED,
210        }
211    }
212    #[doc = "The transmitting signal is not modulated"]
213    #[inline(always)]
214    pub fn is_not_modulated(&self) -> bool {
215        *self == IMS_A::NOT_MODULATED
216    }
217    #[doc = "The transmitting signal is modulated internally"]
218    #[inline(always)]
219    pub fn is_modulated(&self) -> bool {
220        *self == IMS_A::MODULATED
221    }
222}
223#[doc = "Field `ims` writer - Internal Modulation Select"]
224pub type IMS_W<'a, REG> = crate::BitWriter<'a, REG, IMS_A>;
225impl<'a, REG> IMS_W<'a, REG>
226where
227    REG: crate::Writable + crate::RegisterSpec,
228{
229    #[doc = "The transmitting signal is not modulated"]
230    #[inline(always)]
231    pub fn not_modulated(self) -> &'a mut crate::W<REG> {
232        self.variant(IMS_A::NOT_MODULATED)
233    }
234    #[doc = "The transmitting signal is modulated internally"]
235    #[inline(always)]
236    pub fn modulated(self) -> &'a mut crate::W<REG> {
237        self.variant(IMS_A::MODULATED)
238    }
239}
240impl R {
241    #[doc = "Bit 0 - Transmit Block Enable"]
242    #[inline(always)]
243    pub fn txen(&self) -> TXEN_R {
244        TXEN_R::new((self.bits & 1) != 0)
245    }
246    #[doc = "Bit 1 - Transmit Reset\n\nWhen this bit is set, the transmitting is reset. The FIFO will be flushed, the TIC filed and the CSS field will be cleared during Transmit Reset. This field will automatically be cleared when the Transmit Reset is finished, and the CIR transmitter will state Idle."]
247    #[inline(always)]
248    pub fn tr(&self) -> TR_R {
249        TR_R::new(((self.bits >> 1) & 1) != 0)
250    }
251    #[doc = "Bit 2 - Transmit Pulse Polarity Invert"]
252    #[inline(always)]
253    pub fn tppi(&self) -> TPPI_R {
254        TPPI_R::new(((self.bits >> 2) & 1) != 0)
255    }
256    #[doc = "Bits 5:6 - Duty ratio of modulated carrier is high level/low level."]
257    #[inline(always)]
258    pub fn drmc(&self) -> DRMC_R {
259        DRMC_R::new(((self.bits >> 5) & 3) as u8)
260    }
261    #[doc = "Bit 7 - Internal Modulation Select"]
262    #[inline(always)]
263    pub fn ims(&self) -> IMS_R {
264        IMS_R::new(((self.bits >> 7) & 1) != 0)
265    }
266}
267impl W {
268    #[doc = "Bit 0 - Transmit Block Enable"]
269    #[inline(always)]
270    #[must_use]
271    pub fn txen(&mut self) -> TXEN_W<CIR_TGLR_SPEC> {
272        TXEN_W::new(self, 0)
273    }
274    #[doc = "Bit 1 - Transmit Reset\n\nWhen this bit is set, the transmitting is reset. The FIFO will be flushed, the TIC filed and the CSS field will be cleared during Transmit Reset. This field will automatically be cleared when the Transmit Reset is finished, and the CIR transmitter will state Idle."]
275    #[inline(always)]
276    #[must_use]
277    pub fn tr(&mut self) -> TR_W<CIR_TGLR_SPEC> {
278        TR_W::new(self, 1)
279    }
280    #[doc = "Bit 2 - Transmit Pulse Polarity Invert"]
281    #[inline(always)]
282    #[must_use]
283    pub fn tppi(&mut self) -> TPPI_W<CIR_TGLR_SPEC> {
284        TPPI_W::new(self, 2)
285    }
286    #[doc = "Bits 5:6 - Duty ratio of modulated carrier is high level/low level."]
287    #[inline(always)]
288    #[must_use]
289    pub fn drmc(&mut self) -> DRMC_W<CIR_TGLR_SPEC> {
290        DRMC_W::new(self, 5)
291    }
292    #[doc = "Bit 7 - Internal Modulation Select"]
293    #[inline(always)]
294    #[must_use]
295    pub fn ims(&mut self) -> IMS_W<CIR_TGLR_SPEC> {
296        IMS_W::new(self, 7)
297    }
298    #[doc = r" Writes raw bits to the register."]
299    #[doc = r""]
300    #[doc = r" # Safety"]
301    #[doc = r""]
302    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
303    #[inline(always)]
304    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
305        self.bits = bits;
306        self
307    }
308}
309#[doc = "CIR Transmit Global Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_tglr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_tglr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
310pub struct CIR_TGLR_SPEC;
311impl crate::RegisterSpec for CIR_TGLR_SPEC {
312    type Ux = u32;
313}
314#[doc = "`read()` method returns [`cir_tglr::R`](R) reader structure"]
315impl crate::Readable for CIR_TGLR_SPEC {}
316#[doc = "`write(|w| ..)` method takes [`cir_tglr::W`](W) writer structure"]
317impl crate::Writable for CIR_TGLR_SPEC {
318    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
319    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
320}
321#[doc = "`reset()` method sets cir_tglr to value 0"]
322impl crate::Resettable for CIR_TGLR_SPEC {
323    const RESET_VALUE: Self::Ux = 0;
324}
d1_pac/cir_tx/cir_tglr.rs

d1_pac/cir_tx/
cir_tglr.rs
