d1_pac/cir_tx/
cir_tcr.rs

1#[doc = "Register `cir_tcr` reader"]
2pub type R = crate::R<CIR_TCR_SPEC>;
3#[doc = "Register `cir_tcr` writer"]
4pub type W = crate::W<CIR_TCR_SPEC>;
5#[doc = "Field `tts` reader - Type of the transmission signal"]
6pub type TTS_R = crate::BitReader<TTS_A>;
7#[doc = "Type of the transmission signal\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TTS_A {
10    #[doc = "0: The transmitting wave is a single non-cyclical pulse."]
11    NON_CYCLICAL = 0,
12    #[doc = "1: The transmitting wave is a cyclical short-pulse."]
13    CYCLICAL = 1,
14}
15impl From<TTS_A> for bool {
16    #[inline(always)]
17    fn from(variant: TTS_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl TTS_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> TTS_A {
25        match self.bits {
26            false => TTS_A::NON_CYCLICAL,
27            true => TTS_A::CYCLICAL,
28        }
29    }
30    #[doc = "The transmitting wave is a single non-cyclical pulse."]
31    #[inline(always)]
32    pub fn is_non_cyclical(&self) -> bool {
33        *self == TTS_A::NON_CYCLICAL
34    }
35    #[doc = "The transmitting wave is a cyclical short-pulse."]
36    #[inline(always)]
37    pub fn is_cyclical(&self) -> bool {
38        *self == TTS_A::CYCLICAL
39    }
40}
41#[doc = "Field `tts` writer - Type of the transmission signal"]
42pub type TTS_W<'a, REG> = crate::BitWriter<'a, REG, TTS_A>;
43impl<'a, REG> TTS_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "The transmitting wave is a single non-cyclical pulse."]
48    #[inline(always)]
49    pub fn non_cyclical(self) -> &'a mut crate::W<REG> {
50        self.variant(TTS_A::NON_CYCLICAL)
51    }
52    #[doc = "The transmitting wave is a cyclical short-pulse."]
53    #[inline(always)]
54    pub fn cyclical(self) -> &'a mut crate::W<REG> {
55        self.variant(TTS_A::CYCLICAL)
56    }
57}
58#[doc = "Field `rcs` reader - Reference Clock Select for CIR Transmit\n\nThe data in TX_FIFO is used to describe the pulse in Run-Length Code. The basic unit of pulse width is Reference Clock."]
59pub type RCS_R = crate::FieldReader<RCS_A>;
60#[doc = "Reference Clock Select for CIR Transmit\n\nThe data in TX_FIFO is used to describe the pulse in Run-Length Code. The basic unit of pulse width is Reference Clock.\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62#[repr(u8)]
63pub enum RCS_A {
64    #[doc = "0: CIR Transmit reference clock is ir_clk"]
65    IR_CLK = 0,
66    #[doc = "1: CIR Transmit reference clock is ir_clk/2"]
67    IR_CLK_2 = 1,
68    #[doc = "2: CIR Transmit reference clock is ir_clk/4"]
69    IR_CLK_4 = 2,
70    #[doc = "3: CIR Transmit reference clock is ir_clk/8"]
71    IR_CLK_8 = 3,
72    #[doc = "4: CIR Transmit reference clock is ir_clk/64"]
73    IR_CLK_64 = 4,
74    #[doc = "5: CIR Transmit reference clock is ir_clk/128"]
75    IR_CLK_128 = 5,
76    #[doc = "6: CIR Transmit reference clock is ir_clk/256"]
77    IR_CLK_256 = 6,
78    #[doc = "7: CIR Transmit reference clock is ir_clk/512"]
79    IR_CLK_512 = 7,
80}
81impl From<RCS_A> for u8 {
82    #[inline(always)]
83    fn from(variant: RCS_A) -> Self {
84        variant as _
85    }
86}
87impl crate::FieldSpec for RCS_A {
88    type Ux = u8;
89}
90impl RCS_R {
91    #[doc = "Get enumerated values variant"]
92    #[inline(always)]
93    pub const fn variant(&self) -> RCS_A {
94        match self.bits {
95            0 => RCS_A::IR_CLK,
96            1 => RCS_A::IR_CLK_2,
97            2 => RCS_A::IR_CLK_4,
98            3 => RCS_A::IR_CLK_8,
99            4 => RCS_A::IR_CLK_64,
100            5 => RCS_A::IR_CLK_128,
101            6 => RCS_A::IR_CLK_256,
102            7 => RCS_A::IR_CLK_512,
103            _ => unreachable!(),
104        }
105    }
106    #[doc = "CIR Transmit reference clock is ir_clk"]
107    #[inline(always)]
108    pub fn is_ir_clk(&self) -> bool {
109        *self == RCS_A::IR_CLK
110    }
111    #[doc = "CIR Transmit reference clock is ir_clk/2"]
112    #[inline(always)]
113    pub fn is_ir_clk_2(&self) -> bool {
114        *self == RCS_A::IR_CLK_2
115    }
116    #[doc = "CIR Transmit reference clock is ir_clk/4"]
117    #[inline(always)]
118    pub fn is_ir_clk_4(&self) -> bool {
119        *self == RCS_A::IR_CLK_4
120    }
121    #[doc = "CIR Transmit reference clock is ir_clk/8"]
122    #[inline(always)]
123    pub fn is_ir_clk_8(&self) -> bool {
124        *self == RCS_A::IR_CLK_8
125    }
126    #[doc = "CIR Transmit reference clock is ir_clk/64"]
127    #[inline(always)]
128    pub fn is_ir_clk_64(&self) -> bool {
129        *self == RCS_A::IR_CLK_64
130    }
131    #[doc = "CIR Transmit reference clock is ir_clk/128"]
132    #[inline(always)]
133    pub fn is_ir_clk_128(&self) -> bool {
134        *self == RCS_A::IR_CLK_128
135    }
136    #[doc = "CIR Transmit reference clock is ir_clk/256"]
137    #[inline(always)]
138    pub fn is_ir_clk_256(&self) -> bool {
139        *self == RCS_A::IR_CLK_256
140    }
141    #[doc = "CIR Transmit reference clock is ir_clk/512"]
142    #[inline(always)]
143    pub fn is_ir_clk_512(&self) -> bool {
144        *self == RCS_A::IR_CLK_512
145    }
146}
147#[doc = "Field `rcs` writer - Reference Clock Select for CIR Transmit\n\nThe data in TX_FIFO is used to describe the pulse in Run-Length Code. The basic unit of pulse width is Reference Clock."]
148pub type RCS_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 3, RCS_A>;
149impl<'a, REG> RCS_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152    REG::Ux: From<u8>,
153{
154    #[doc = "CIR Transmit reference clock is ir_clk"]
155    #[inline(always)]
156    pub fn ir_clk(self) -> &'a mut crate::W<REG> {
157        self.variant(RCS_A::IR_CLK)
158    }
159    #[doc = "CIR Transmit reference clock is ir_clk/2"]
160    #[inline(always)]
161    pub fn ir_clk_2(self) -> &'a mut crate::W<REG> {
162        self.variant(RCS_A::IR_CLK_2)
163    }
164    #[doc = "CIR Transmit reference clock is ir_clk/4"]
165    #[inline(always)]
166    pub fn ir_clk_4(self) -> &'a mut crate::W<REG> {
167        self.variant(RCS_A::IR_CLK_4)
168    }
169    #[doc = "CIR Transmit reference clock is ir_clk/8"]
170    #[inline(always)]
171    pub fn ir_clk_8(self) -> &'a mut crate::W<REG> {
172        self.variant(RCS_A::IR_CLK_8)
173    }
174    #[doc = "CIR Transmit reference clock is ir_clk/64"]
175    #[inline(always)]
176    pub fn ir_clk_64(self) -> &'a mut crate::W<REG> {
177        self.variant(RCS_A::IR_CLK_64)
178    }
179    #[doc = "CIR Transmit reference clock is ir_clk/128"]
180    #[inline(always)]
181    pub fn ir_clk_128(self) -> &'a mut crate::W<REG> {
182        self.variant(RCS_A::IR_CLK_128)
183    }
184    #[doc = "CIR Transmit reference clock is ir_clk/256"]
185    #[inline(always)]
186    pub fn ir_clk_256(self) -> &'a mut crate::W<REG> {
187        self.variant(RCS_A::IR_CLK_256)
188    }
189    #[doc = "CIR Transmit reference clock is ir_clk/512"]
190    #[inline(always)]
191    pub fn ir_clk_512(self) -> &'a mut crate::W<REG> {
192        self.variant(RCS_A::IR_CLK_512)
193    }
194}
195#[doc = "Field `css` reader - Cyclical Pulse Start/Stop Control"]
196pub type CSS_R = crate::BitReader<CSS_A>;
197#[doc = "Cyclical Pulse Start/Stop Control\n\nValue on reset: 0"]
198#[derive(Clone, Copy, Debug, PartialEq, Eq)]
199pub enum CSS_A {
200    #[doc = "0: Stop when cleared to '0'. From start to stop, all data in FIFO must be transmitted."]
201    STOP = 0,
202    #[doc = "1: Start. Start to transmit when it is set to '1'."]
203    START = 1,
204}
205impl From<CSS_A> for bool {
206    #[inline(always)]
207    fn from(variant: CSS_A) -> Self {
208        variant as u8 != 0
209    }
210}
211impl CSS_R {
212    #[doc = "Get enumerated values variant"]
213    #[inline(always)]
214    pub const fn variant(&self) -> CSS_A {
215        match self.bits {
216            false => CSS_A::STOP,
217            true => CSS_A::START,
218        }
219    }
220    #[doc = "Stop when cleared to '0'. From start to stop, all data in FIFO must be transmitted."]
221    #[inline(always)]
222    pub fn is_stop(&self) -> bool {
223        *self == CSS_A::STOP
224    }
225    #[doc = "Start. Start to transmit when it is set to '1'."]
226    #[inline(always)]
227    pub fn is_start(&self) -> bool {
228        *self == CSS_A::START
229    }
230}
231#[doc = "Field `css` writer - Cyclical Pulse Start/Stop Control"]
232pub type CSS_W<'a, REG> = crate::BitWriter<'a, REG, CSS_A>;
233impl<'a, REG> CSS_W<'a, REG>
234where
235    REG: crate::Writable + crate::RegisterSpec,
236{
237    #[doc = "Stop when cleared to '0'. From start to stop, all data in FIFO must be transmitted."]
238    #[inline(always)]
239    pub fn stop(self) -> &'a mut crate::W<REG> {
240        self.variant(CSS_A::STOP)
241    }
242    #[doc = "Start. Start to transmit when it is set to '1'."]
243    #[inline(always)]
244    pub fn start(self) -> &'a mut crate::W<REG> {
245        self.variant(CSS_A::START)
246    }
247}
248impl R {
249    #[doc = "Bit 0 - Type of the transmission signal"]
250    #[inline(always)]
251    pub fn tts(&self) -> TTS_R {
252        TTS_R::new((self.bits & 1) != 0)
253    }
254    #[doc = "Bits 1:3 - Reference Clock Select for CIR Transmit\n\nThe data in TX_FIFO is used to describe the pulse in Run-Length Code. The basic unit of pulse width is Reference Clock."]
255    #[inline(always)]
256    pub fn rcs(&self) -> RCS_R {
257        RCS_R::new(((self.bits >> 1) & 7) as u8)
258    }
259    #[doc = "Bit 7 - Cyclical Pulse Start/Stop Control"]
260    #[inline(always)]
261    pub fn css(&self) -> CSS_R {
262        CSS_R::new(((self.bits >> 7) & 1) != 0)
263    }
264}
265impl W {
266    #[doc = "Bit 0 - Type of the transmission signal"]
267    #[inline(always)]
268    #[must_use]
269    pub fn tts(&mut self) -> TTS_W<CIR_TCR_SPEC> {
270        TTS_W::new(self, 0)
271    }
272    #[doc = "Bits 1:3 - Reference Clock Select for CIR Transmit\n\nThe data in TX_FIFO is used to describe the pulse in Run-Length Code. The basic unit of pulse width is Reference Clock."]
273    #[inline(always)]
274    #[must_use]
275    pub fn rcs(&mut self) -> RCS_W<CIR_TCR_SPEC> {
276        RCS_W::new(self, 1)
277    }
278    #[doc = "Bit 7 - Cyclical Pulse Start/Stop Control"]
279    #[inline(always)]
280    #[must_use]
281    pub fn css(&mut self) -> CSS_W<CIR_TCR_SPEC> {
282        CSS_W::new(self, 7)
283    }
284    #[doc = r" Writes raw bits to the register."]
285    #[doc = r""]
286    #[doc = r" # Safety"]
287    #[doc = r""]
288    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
289    #[inline(always)]
290    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
291        self.bits = bits;
292        self
293    }
294}
295#[doc = "CIR Transmit Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_tcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
296pub struct CIR_TCR_SPEC;
297impl crate::RegisterSpec for CIR_TCR_SPEC {
298    type Ux = u32;
299}
300#[doc = "`read()` method returns [`cir_tcr::R`](R) reader structure"]
301impl crate::Readable for CIR_TCR_SPEC {}
302#[doc = "`write(|w| ..)` method takes [`cir_tcr::W`](W) writer structure"]
303impl crate::Writable for CIR_TCR_SPEC {
304    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
305    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
306}
307#[doc = "`reset()` method sets cir_tcr to value 0"]
308impl crate::Resettable for CIR_TCR_SPEC {
309    const RESET_VALUE: Self::Ux = 0;
310}
d1_pac/cir_tx/cir_tcr.rs

d1_pac/cir_tx/
cir_tcr.rs
