d1_pac/cir_rx/
cir_rxint.rs

1#[doc = "Register `cir_rxint` reader"]
2pub type R = crate::R<CIR_RXINT_SPEC>;
3#[doc = "Register `cir_rxint` writer"]
4pub type W = crate::W<CIR_RXINT_SPEC>;
5#[doc = "Field `roi_en` reader - Receiver FIFO Overrun Interrupt Enable"]
6pub type ROI_EN_R = crate::BitReader<ROI_EN_A>;
7#[doc = "Receiver FIFO Overrun Interrupt Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum ROI_EN_A {
10    #[doc = "0: Disable"]
11    DISABLE = 0,
12    #[doc = "1: Enable"]
13    ENABLE = 1,
14}
15impl From<ROI_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: ROI_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl ROI_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> ROI_EN_A {
25        match self.bits {
26            false => ROI_EN_A::DISABLE,
27            true => ROI_EN_A::ENABLE,
28        }
29    }
30    #[doc = "Disable"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == ROI_EN_A::DISABLE
34    }
35    #[doc = "Enable"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == ROI_EN_A::ENABLE
39    }
40}
41#[doc = "Field `roi_en` writer - Receiver FIFO Overrun Interrupt Enable"]
42pub type ROI_EN_W<'a, REG> = crate::BitWriter<'a, REG, ROI_EN_A>;
43impl<'a, REG> ROI_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(ROI_EN_A::DISABLE)
51    }
52    #[doc = "Enable"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(ROI_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `rpei_en` reader - Receiver Packet End Interrupt Enable"]
59pub type RPEI_EN_R = crate::BitReader<RPEI_EN_A>;
60#[doc = "Receiver Packet End Interrupt Enable\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum RPEI_EN_A {
63    #[doc = "0: Disable"]
64    DISABLE = 0,
65    #[doc = "1: Enable"]
66    ENABLE = 1,
67}
68impl From<RPEI_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: RPEI_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl RPEI_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> RPEI_EN_A {
78        match self.bits {
79            false => RPEI_EN_A::DISABLE,
80            true => RPEI_EN_A::ENABLE,
81        }
82    }
83    #[doc = "Disable"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == RPEI_EN_A::DISABLE
87    }
88    #[doc = "Enable"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == RPEI_EN_A::ENABLE
92    }
93}
94#[doc = "Field `rpei_en` writer - Receiver Packet End Interrupt Enable"]
95pub type RPEI_EN_W<'a, REG> = crate::BitWriter<'a, REG, RPEI_EN_A>;
96impl<'a, REG> RPEI_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Disable"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(RPEI_EN_A::DISABLE)
104    }
105    #[doc = "Enable"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(RPEI_EN_A::ENABLE)
109    }
110}
111#[doc = "Field `rai_en` reader - RX FIFO Available Interrupt Enable"]
112pub type RAI_EN_R = crate::BitReader<RAI_EN_A>;
113#[doc = "RX FIFO Available Interrupt Enable\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum RAI_EN_A {
116    #[doc = "0: Disable"]
117    DISABLE = 0,
118    #[doc = "1: Enable"]
119    ENABLE = 1,
120}
121impl From<RAI_EN_A> for bool {
122    #[inline(always)]
123    fn from(variant: RAI_EN_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl RAI_EN_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> RAI_EN_A {
131        match self.bits {
132            false => RAI_EN_A::DISABLE,
133            true => RAI_EN_A::ENABLE,
134        }
135    }
136    #[doc = "Disable"]
137    #[inline(always)]
138    pub fn is_disable(&self) -> bool {
139        *self == RAI_EN_A::DISABLE
140    }
141    #[doc = "Enable"]
142    #[inline(always)]
143    pub fn is_enable(&self) -> bool {
144        *self == RAI_EN_A::ENABLE
145    }
146}
147#[doc = "Field `rai_en` writer - RX FIFO Available Interrupt Enable"]
148pub type RAI_EN_W<'a, REG> = crate::BitWriter<'a, REG, RAI_EN_A>;
149impl<'a, REG> RAI_EN_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Disable"]
154    #[inline(always)]
155    pub fn disable(self) -> &'a mut crate::W<REG> {
156        self.variant(RAI_EN_A::DISABLE)
157    }
158    #[doc = "Enable"]
159    #[inline(always)]
160    pub fn enable(self) -> &'a mut crate::W<REG> {
161        self.variant(RAI_EN_A::ENABLE)
162    }
163}
164#[doc = "Field `drq_en` reader - RX FIFO DMA Enable"]
165pub type DRQ_EN_R = crate::BitReader<DRQ_EN_A>;
166#[doc = "RX FIFO DMA Enable\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum DRQ_EN_A {
169    #[doc = "0: Disable"]
170    DISABLE = 0,
171    #[doc = "1: Enable"]
172    ENABLE = 1,
173}
174impl From<DRQ_EN_A> for bool {
175    #[inline(always)]
176    fn from(variant: DRQ_EN_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl DRQ_EN_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> DRQ_EN_A {
184        match self.bits {
185            false => DRQ_EN_A::DISABLE,
186            true => DRQ_EN_A::ENABLE,
187        }
188    }
189    #[doc = "Disable"]
190    #[inline(always)]
191    pub fn is_disable(&self) -> bool {
192        *self == DRQ_EN_A::DISABLE
193    }
194    #[doc = "Enable"]
195    #[inline(always)]
196    pub fn is_enable(&self) -> bool {
197        *self == DRQ_EN_A::ENABLE
198    }
199}
200#[doc = "Field `drq_en` writer - RX FIFO DMA Enable"]
201pub type DRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, DRQ_EN_A>;
202impl<'a, REG> DRQ_EN_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "Disable"]
207    #[inline(always)]
208    pub fn disable(self) -> &'a mut crate::W<REG> {
209        self.variant(DRQ_EN_A::DISABLE)
210    }
211    #[doc = "Enable"]
212    #[inline(always)]
213    pub fn enable(self) -> &'a mut crate::W<REG> {
214        self.variant(DRQ_EN_A::ENABLE)
215    }
216}
217#[doc = "Field `ral` reader - RX FIFO available received byte level for interrupt and DMA request\n\nTRIGGER_LEVEL = RAL + 1"]
218pub type RAL_R = crate::FieldReader;
219#[doc = "Field `ral` writer - RX FIFO available received byte level for interrupt and DMA request\n\nTRIGGER_LEVEL = RAL + 1"]
220pub type RAL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
221impl R {
222    #[doc = "Bit 0 - Receiver FIFO Overrun Interrupt Enable"]
223    #[inline(always)]
224    pub fn roi_en(&self) -> ROI_EN_R {
225        ROI_EN_R::new((self.bits & 1) != 0)
226    }
227    #[doc = "Bit 1 - Receiver Packet End Interrupt Enable"]
228    #[inline(always)]
229    pub fn rpei_en(&self) -> RPEI_EN_R {
230        RPEI_EN_R::new(((self.bits >> 1) & 1) != 0)
231    }
232    #[doc = "Bit 4 - RX FIFO Available Interrupt Enable"]
233    #[inline(always)]
234    pub fn rai_en(&self) -> RAI_EN_R {
235        RAI_EN_R::new(((self.bits >> 4) & 1) != 0)
236    }
237    #[doc = "Bit 5 - RX FIFO DMA Enable"]
238    #[inline(always)]
239    pub fn drq_en(&self) -> DRQ_EN_R {
240        DRQ_EN_R::new(((self.bits >> 5) & 1) != 0)
241    }
242    #[doc = "Bits 8:13 - RX FIFO available received byte level for interrupt and DMA request\n\nTRIGGER_LEVEL = RAL + 1"]
243    #[inline(always)]
244    pub fn ral(&self) -> RAL_R {
245        RAL_R::new(((self.bits >> 8) & 0x3f) as u8)
246    }
247}
248impl W {
249    #[doc = "Bit 0 - Receiver FIFO Overrun Interrupt Enable"]
250    #[inline(always)]
251    #[must_use]
252    pub fn roi_en(&mut self) -> ROI_EN_W<CIR_RXINT_SPEC> {
253        ROI_EN_W::new(self, 0)
254    }
255    #[doc = "Bit 1 - Receiver Packet End Interrupt Enable"]
256    #[inline(always)]
257    #[must_use]
258    pub fn rpei_en(&mut self) -> RPEI_EN_W<CIR_RXINT_SPEC> {
259        RPEI_EN_W::new(self, 1)
260    }
261    #[doc = "Bit 4 - RX FIFO Available Interrupt Enable"]
262    #[inline(always)]
263    #[must_use]
264    pub fn rai_en(&mut self) -> RAI_EN_W<CIR_RXINT_SPEC> {
265        RAI_EN_W::new(self, 4)
266    }
267    #[doc = "Bit 5 - RX FIFO DMA Enable"]
268    #[inline(always)]
269    #[must_use]
270    pub fn drq_en(&mut self) -> DRQ_EN_W<CIR_RXINT_SPEC> {
271        DRQ_EN_W::new(self, 5)
272    }
273    #[doc = "Bits 8:13 - RX FIFO available received byte level for interrupt and DMA request\n\nTRIGGER_LEVEL = RAL + 1"]
274    #[inline(always)]
275    #[must_use]
276    pub fn ral(&mut self) -> RAL_W<CIR_RXINT_SPEC> {
277        RAL_W::new(self, 8)
278    }
279    #[doc = r" Writes raw bits to the register."]
280    #[doc = r""]
281    #[doc = r" # Safety"]
282    #[doc = r""]
283    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
284    #[inline(always)]
285    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
286        self.bits = bits;
287        self
288    }
289}
290#[doc = "CIR Receiver Interrupt Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_rxint::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_rxint::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
291pub struct CIR_RXINT_SPEC;
292impl crate::RegisterSpec for CIR_RXINT_SPEC {
293    type Ux = u32;
294}
295#[doc = "`read()` method returns [`cir_rxint::R`](R) reader structure"]
296impl crate::Readable for CIR_RXINT_SPEC {}
297#[doc = "`write(|w| ..)` method takes [`cir_rxint::W`](W) writer structure"]
298impl crate::Writable for CIR_RXINT_SPEC {
299    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
300    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
301}
302#[doc = "`reset()` method sets cir_rxint to value 0"]
303impl crate::Resettable for CIR_RXINT_SPEC {
304    const RESET_VALUE: Self::Ux = 0;
305}
d1_pac/cir_rx/cir_rxint.rs

d1_pac/cir_rx/
cir_rxint.rs
