d1_pac/cir_rx/
cir_ctl.rs

1#[doc = "Register `cir_ctl` reader"]
2pub type R = crate::R<CIR_CTL_SPEC>;
3#[doc = "Register `cir_ctl` writer"]
4pub type W = crate::W<CIR_CTL_SPEC>;
5#[doc = "Field `gen` reader - Global Enable\n\nA disable on this bit overrides any other block or channel enables and flushes all FIFOs."]
6pub type GEN_R = crate::BitReader<GEN_A>;
7#[doc = "Global Enable\n\nA disable on this bit overrides any other block or channel enables and flushes all FIFOs.\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum GEN_A {
10    #[doc = "0: Disable"]
11    DISABLE = 0,
12    #[doc = "1: Enable"]
13    ENABLE = 1,
14}
15impl From<GEN_A> for bool {
16    #[inline(always)]
17    fn from(variant: GEN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl GEN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> GEN_A {
25        match self.bits {
26            false => GEN_A::DISABLE,
27            true => GEN_A::ENABLE,
28        }
29    }
30    #[doc = "Disable"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == GEN_A::DISABLE
34    }
35    #[doc = "Enable"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == GEN_A::ENABLE
39    }
40}
41#[doc = "Field `gen` writer - Global Enable\n\nA disable on this bit overrides any other block or channel enables and flushes all FIFOs."]
42pub type GEN_W<'a, REG> = crate::BitWriter<'a, REG, GEN_A>;
43impl<'a, REG> GEN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(GEN_A::DISABLE)
51    }
52    #[doc = "Enable"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(GEN_A::ENABLE)
56    }
57}
58#[doc = "Field `rxen` reader - Receiver Block Enable"]
59pub type RXEN_R = crate::BitReader<RXEN_A>;
60#[doc = "Receiver Block Enable\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum RXEN_A {
63    #[doc = "0: Disable"]
64    DISABLE = 0,
65    #[doc = "1: Enable"]
66    ENABLE = 1,
67}
68impl From<RXEN_A> for bool {
69    #[inline(always)]
70    fn from(variant: RXEN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl RXEN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> RXEN_A {
78        match self.bits {
79            false => RXEN_A::DISABLE,
80            true => RXEN_A::ENABLE,
81        }
82    }
83    #[doc = "Disable"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == RXEN_A::DISABLE
87    }
88    #[doc = "Enable"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == RXEN_A::ENABLE
92    }
93}
94#[doc = "Field `rxen` writer - Receiver Block Enable"]
95pub type RXEN_W<'a, REG> = crate::BitWriter<'a, REG, RXEN_A>;
96impl<'a, REG> RXEN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Disable"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(RXEN_A::DISABLE)
104    }
105    #[doc = "Enable"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(RXEN_A::ENABLE)
109    }
110}
111#[doc = "Field `ciren` reader - CIR Enable"]
112pub type CIREN_R = crate::FieldReader<CIREN_A>;
113#[doc = "CIR Enable\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115#[repr(u8)]
116pub enum CIREN_A {
117    #[doc = "3: CIR mode enable"]
118    ENABLE = 3,
119}
120impl From<CIREN_A> for u8 {
121    #[inline(always)]
122    fn from(variant: CIREN_A) -> Self {
123        variant as _
124    }
125}
126impl crate::FieldSpec for CIREN_A {
127    type Ux = u8;
128}
129impl CIREN_R {
130    #[doc = "Get enumerated values variant"]
131    #[inline(always)]
132    pub const fn variant(&self) -> Option<CIREN_A> {
133        match self.bits {
134            3 => Some(CIREN_A::ENABLE),
135            _ => None,
136        }
137    }
138    #[doc = "CIR mode enable"]
139    #[inline(always)]
140    pub fn is_enable(&self) -> bool {
141        *self == CIREN_A::ENABLE
142    }
143}
144#[doc = "Field `ciren` writer - CIR Enable"]
145pub type CIREN_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CIREN_A>;
146impl<'a, REG> CIREN_W<'a, REG>
147where
148    REG: crate::Writable + crate::RegisterSpec,
149    REG::Ux: From<u8>,
150{
151    #[doc = "CIR mode enable"]
152    #[inline(always)]
153    pub fn enable(self) -> &'a mut crate::W<REG> {
154        self.variant(CIREN_A::ENABLE)
155    }
156}
157#[doc = "Field `apam` reader - Active Pulse Accept Mode"]
158pub type APAM_R = crate::FieldReader<APAM_A>;
159#[doc = "Active Pulse Accept Mode\n\nValue on reset: 0"]
160#[derive(Clone, Copy, Debug, PartialEq, Eq)]
161#[repr(u8)]
162pub enum APAM_A {
163    #[doc = "0: Both positive and negative pulses are valid as a leading code"]
164    BOTH_VALID = 0,
165    #[doc = "2: Only negative pulse is valid as a leading code"]
166    ONLY_NEGATIVE = 2,
167    #[doc = "3: Only positive pulse is valid as a leading code"]
168    ONLY_POSITIVE = 3,
169}
170impl From<APAM_A> for u8 {
171    #[inline(always)]
172    fn from(variant: APAM_A) -> Self {
173        variant as _
174    }
175}
176impl crate::FieldSpec for APAM_A {
177    type Ux = u8;
178}
179impl APAM_R {
180    #[doc = "Get enumerated values variant"]
181    #[inline(always)]
182    pub const fn variant(&self) -> Option<APAM_A> {
183        match self.bits {
184            0 => Some(APAM_A::BOTH_VALID),
185            2 => Some(APAM_A::ONLY_NEGATIVE),
186            3 => Some(APAM_A::ONLY_POSITIVE),
187            _ => None,
188        }
189    }
190    #[doc = "Both positive and negative pulses are valid as a leading code"]
191    #[inline(always)]
192    pub fn is_both_valid(&self) -> bool {
193        *self == APAM_A::BOTH_VALID
194    }
195    #[doc = "Only negative pulse is valid as a leading code"]
196    #[inline(always)]
197    pub fn is_only_negative(&self) -> bool {
198        *self == APAM_A::ONLY_NEGATIVE
199    }
200    #[doc = "Only positive pulse is valid as a leading code"]
201    #[inline(always)]
202    pub fn is_only_positive(&self) -> bool {
203        *self == APAM_A::ONLY_POSITIVE
204    }
205}
206#[doc = "Field `apam` writer - Active Pulse Accept Mode"]
207pub type APAM_W<'a, REG> = crate::FieldWriter<'a, REG, 2, APAM_A>;
208impl<'a, REG> APAM_W<'a, REG>
209where
210    REG: crate::Writable + crate::RegisterSpec,
211    REG::Ux: From<u8>,
212{
213    #[doc = "Both positive and negative pulses are valid as a leading code"]
214    #[inline(always)]
215    pub fn both_valid(self) -> &'a mut crate::W<REG> {
216        self.variant(APAM_A::BOTH_VALID)
217    }
218    #[doc = "Only negative pulse is valid as a leading code"]
219    #[inline(always)]
220    pub fn only_negative(self) -> &'a mut crate::W<REG> {
221        self.variant(APAM_A::ONLY_NEGATIVE)
222    }
223    #[doc = "Only positive pulse is valid as a leading code"]
224    #[inline(always)]
225    pub fn only_positive(self) -> &'a mut crate::W<REG> {
226        self.variant(APAM_A::ONLY_POSITIVE)
227    }
228}
229impl R {
230    #[doc = "Bit 0 - Global Enable\n\nA disable on this bit overrides any other block or channel enables and flushes all FIFOs."]
231    #[inline(always)]
232    pub fn gen(&self) -> GEN_R {
233        GEN_R::new((self.bits & 1) != 0)
234    }
235    #[doc = "Bit 1 - Receiver Block Enable"]
236    #[inline(always)]
237    pub fn rxen(&self) -> RXEN_R {
238        RXEN_R::new(((self.bits >> 1) & 1) != 0)
239    }
240    #[doc = "Bits 4:5 - CIR Enable"]
241    #[inline(always)]
242    pub fn ciren(&self) -> CIREN_R {
243        CIREN_R::new(((self.bits >> 4) & 3) as u8)
244    }
245    #[doc = "Bits 6:7 - Active Pulse Accept Mode"]
246    #[inline(always)]
247    pub fn apam(&self) -> APAM_R {
248        APAM_R::new(((self.bits >> 6) & 3) as u8)
249    }
250}
251impl W {
252    #[doc = "Bit 0 - Global Enable\n\nA disable on this bit overrides any other block or channel enables and flushes all FIFOs."]
253    #[inline(always)]
254    #[must_use]
255    pub fn gen(&mut self) -> GEN_W<CIR_CTL_SPEC> {
256        GEN_W::new(self, 0)
257    }
258    #[doc = "Bit 1 - Receiver Block Enable"]
259    #[inline(always)]
260    #[must_use]
261    pub fn rxen(&mut self) -> RXEN_W<CIR_CTL_SPEC> {
262        RXEN_W::new(self, 1)
263    }
264    #[doc = "Bits 4:5 - CIR Enable"]
265    #[inline(always)]
266    #[must_use]
267    pub fn ciren(&mut self) -> CIREN_W<CIR_CTL_SPEC> {
268        CIREN_W::new(self, 4)
269    }
270    #[doc = "Bits 6:7 - Active Pulse Accept Mode"]
271    #[inline(always)]
272    #[must_use]
273    pub fn apam(&mut self) -> APAM_W<CIR_CTL_SPEC> {
274        APAM_W::new(self, 6)
275    }
276    #[doc = r" Writes raw bits to the register."]
277    #[doc = r""]
278    #[doc = r" # Safety"]
279    #[doc = r""]
280    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
281    #[inline(always)]
282    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
283        self.bits = bits;
284        self
285    }
286}
287#[doc = "CIR Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cir_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cir_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
288pub struct CIR_CTL_SPEC;
289impl crate::RegisterSpec for CIR_CTL_SPEC {
290    type Ux = u32;
291}
292#[doc = "`read()` method returns [`cir_ctl::R`](R) reader structure"]
293impl crate::Readable for CIR_CTL_SPEC {}
294#[doc = "`write(|w| ..)` method takes [`cir_ctl::W`](W) writer structure"]
295impl crate::Writable for CIR_CTL_SPEC {
296    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
297    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
298}
299#[doc = "`reset()` method sets cir_ctl to value 0"]
300impl crate::Resettable for CIR_CTL_SPEC {
301    const RESET_VALUE: Self::Ux = 0;
302}
d1_pac/cir_rx/cir_ctl.rs

d1_pac/cir_rx/
cir_ctl.rs
