d1_pac/ce_ns/
ce_tlr.rs

1#[doc = "Register `ce_tlr` reader"]
2pub type R = crate::R<CE_TLR_SPEC>;
3#[doc = "Register `ce_tlr` writer"]
4pub type W = crate::W<CE_TLR_SPEC>;
5#[doc = "Field `task_load` reader - Task Load\n\nWhen set, the CE can load the descriptor of task if the task FIFO is not full."]
6pub type TASK_LOAD_R = crate::BitReader;
7#[doc = "Field `task_load` writer - Task Load\n\nWhen set, the CE can load the descriptor of task if the task FIFO is not full."]
8pub type TASK_LOAD_W<'a, REG> = crate::BitWriter<'a, REG>;
9impl R {
10    #[doc = "Bit 0 - Task Load\n\nWhen set, the CE can load the descriptor of task if the task FIFO is not full."]
11    #[inline(always)]
12    pub fn task_load(&self) -> TASK_LOAD_R {
13        TASK_LOAD_R::new((self.bits & 1) != 0)
14    }
15}
16impl W {
17    #[doc = "Bit 0 - Task Load\n\nWhen set, the CE can load the descriptor of task if the task FIFO is not full."]
18    #[inline(always)]
19    #[must_use]
20    pub fn task_load(&mut self) -> TASK_LOAD_W<CE_TLR_SPEC> {
21        TASK_LOAD_W::new(self, 0)
22    }
23    #[doc = r" Writes raw bits to the register."]
24    #[doc = r""]
25    #[doc = r" # Safety"]
26    #[doc = r""]
27    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
28    #[inline(always)]
29    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
30        self.bits = bits;
31        self
32    }
33}
34#[doc = "Task Load Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ce_tlr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ce_tlr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
35pub struct CE_TLR_SPEC;
36impl crate::RegisterSpec for CE_TLR_SPEC {
37    type Ux = u32;
38}
39#[doc = "`read()` method returns [`ce_tlr::R`](R) reader structure"]
40impl crate::Readable for CE_TLR_SPEC {}
41#[doc = "`write(|w| ..)` method takes [`ce_tlr::W`](W) writer structure"]
42impl crate::Writable for CE_TLR_SPEC {
43    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
44    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
45}
46#[doc = "`reset()` method sets ce_tlr to value 0"]
47impl crate::Resettable for CE_TLR_SPEC {
48    const RESET_VALUE: Self::Ux = 0;
49}
d1_pac/ce_ns/ce_tlr.rs

d1_pac/ce_ns/
ce_tlr.rs
