d1_pac/ce_ns/
ce_isr.rs

1#[doc = "Register `ce_isr` reader"]
2pub type R = crate::R<CE_ISR_SPEC>;
3#[doc = "Register `ce_isr` writer"]
4pub type W = crate::W<CE_ISR_SPEC>;
5#[doc = "Field `task_pending[0-3]` reader - Task Channel 3-0 End Pending\n\nIt indicates whether task is completed.\n\nWrite the corresponding channel bit of the register to clear the end flag."]
6pub type TASK_PENDING_R = crate::FieldReader<TASK_PENDING_A>;
7#[doc = "Task Channel 3-0 End Pending\n\nIt indicates whether task is completed.\n\nWrite the corresponding channel bit of the register to clear the end flag.\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum TASK_PENDING_A {
11    #[doc = "0: Task not finished"]
12    NOT_FINISHED = 0,
13    #[doc = "1: Task finished"]
14    FINISHED = 1,
15}
16impl From<TASK_PENDING_A> for u8 {
17    #[inline(always)]
18    fn from(variant: TASK_PENDING_A) -> Self {
19        variant as _
20    }
21}
22impl crate::FieldSpec for TASK_PENDING_A {
23    type Ux = u8;
24}
25impl TASK_PENDING_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> Option<TASK_PENDING_A> {
29        match self.bits {
30            0 => Some(TASK_PENDING_A::NOT_FINISHED),
31            1 => Some(TASK_PENDING_A::FINISHED),
32            _ => None,
33        }
34    }
35    #[doc = "Task not finished"]
36    #[inline(always)]
37    pub fn is_not_finished(&self) -> bool {
38        *self == TASK_PENDING_A::NOT_FINISHED
39    }
40    #[doc = "Task finished"]
41    #[inline(always)]
42    pub fn is_finished(&self) -> bool {
43        *self == TASK_PENDING_A::FINISHED
44    }
45}
46#[doc = "Field `task_pending[0-3]` writer - Task Channel 3-0 End Pending\n\nIt indicates whether task is completed.\n\nWrite the corresponding channel bit of the register to clear the end flag."]
47pub type TASK_PENDING_W<'a, REG> = crate::FieldWriter<'a, REG, 4, TASK_PENDING_A>;
48impl<'a, REG> TASK_PENDING_W<'a, REG>
49where
50    REG: crate::Writable + crate::RegisterSpec,
51    REG::Ux: From<u8>,
52{
53    #[doc = "Task not finished"]
54    #[inline(always)]
55    pub fn not_finished(self) -> &'a mut crate::W<REG> {
56        self.variant(TASK_PENDING_A::NOT_FINISHED)
57    }
58    #[doc = "Task finished"]
59    #[inline(always)]
60    pub fn finished(self) -> &'a mut crate::W<REG> {
61        self.variant(TASK_PENDING_A::FINISHED)
62    }
63}
64impl R {
65    #[doc = "Task Channel 3-0 End Pending\n\nIt indicates whether task is completed.\n\nWrite the corresponding channel bit of the register to clear the end flag.\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `task0_pending` field"]
66    #[inline(always)]
67    pub fn task_pending(&self, n: u8) -> TASK_PENDING_R {
68        #[allow(clippy::no_effect)]
69        [(); 4][n as usize];
70        TASK_PENDING_R::new(((self.bits >> n) & 0x0f) as u8)
71    }
72    #[doc = "Bits 0:3 - Task Channel 3-0 End Pending\n\nIt indicates whether task is completed.\n\nWrite the corresponding channel bit of the register to clear the end flag."]
73    #[inline(always)]
74    pub fn task0_pending(&self) -> TASK_PENDING_R {
75        TASK_PENDING_R::new((self.bits & 0x0f) as u8)
76    }
77    #[doc = "Bits 1:4 - Task Channel 3-0 End Pending\n\nIt indicates whether task is completed.\n\nWrite the corresponding channel bit of the register to clear the end flag."]
78    #[inline(always)]
79    pub fn task1_pending(&self) -> TASK_PENDING_R {
80        TASK_PENDING_R::new(((self.bits >> 1) & 0x0f) as u8)
81    }
82    #[doc = "Bits 2:5 - Task Channel 3-0 End Pending\n\nIt indicates whether task is completed.\n\nWrite the corresponding channel bit of the register to clear the end flag."]
83    #[inline(always)]
84    pub fn task2_pending(&self) -> TASK_PENDING_R {
85        TASK_PENDING_R::new(((self.bits >> 2) & 0x0f) as u8)
86    }
87    #[doc = "Bits 3:6 - Task Channel 3-0 End Pending\n\nIt indicates whether task is completed.\n\nWrite the corresponding channel bit of the register to clear the end flag."]
88    #[inline(always)]
89    pub fn task3_pending(&self) -> TASK_PENDING_R {
90        TASK_PENDING_R::new(((self.bits >> 3) & 0x0f) as u8)
91    }
92}
93impl W {
94    #[doc = "Task Channel 3-0 End Pending\n\nIt indicates whether task is completed.\n\nWrite the corresponding channel bit of the register to clear the end flag.\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `task0_pending` field"]
95    #[inline(always)]
96    #[must_use]
97    pub fn task_pending(&mut self, n: u8) -> TASK_PENDING_W<CE_ISR_SPEC> {
98        #[allow(clippy::no_effect)]
99        [(); 4][n as usize];
100        TASK_PENDING_W::new(self, n)
101    }
102    #[doc = "Bits 0:3 - Task Channel 3-0 End Pending\n\nIt indicates whether task is completed.\n\nWrite the corresponding channel bit of the register to clear the end flag."]
103    #[inline(always)]
104    #[must_use]
105    pub fn task0_pending(&mut self) -> TASK_PENDING_W<CE_ISR_SPEC> {
106        TASK_PENDING_W::new(self, 0)
107    }
108    #[doc = "Bits 1:4 - Task Channel 3-0 End Pending\n\nIt indicates whether task is completed.\n\nWrite the corresponding channel bit of the register to clear the end flag."]
109    #[inline(always)]
110    #[must_use]
111    pub fn task1_pending(&mut self) -> TASK_PENDING_W<CE_ISR_SPEC> {
112        TASK_PENDING_W::new(self, 1)
113    }
114    #[doc = "Bits 2:5 - Task Channel 3-0 End Pending\n\nIt indicates whether task is completed.\n\nWrite the corresponding channel bit of the register to clear the end flag."]
115    #[inline(always)]
116    #[must_use]
117    pub fn task2_pending(&mut self) -> TASK_PENDING_W<CE_ISR_SPEC> {
118        TASK_PENDING_W::new(self, 2)
119    }
120    #[doc = "Bits 3:6 - Task Channel 3-0 End Pending\n\nIt indicates whether task is completed.\n\nWrite the corresponding channel bit of the register to clear the end flag."]
121    #[inline(always)]
122    #[must_use]
123    pub fn task3_pending(&mut self) -> TASK_PENDING_W<CE_ISR_SPEC> {
124        TASK_PENDING_W::new(self, 3)
125    }
126    #[doc = r" Writes raw bits to the register."]
127    #[doc = r""]
128    #[doc = r" # Safety"]
129    #[doc = r""]
130    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
131    #[inline(always)]
132    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
133        self.bits = bits;
134        self
135    }
136}
137#[doc = "Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ce_isr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ce_isr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
138pub struct CE_ISR_SPEC;
139impl crate::RegisterSpec for CE_ISR_SPEC {
140    type Ux = u32;
141}
142#[doc = "`read()` method returns [`ce_isr::R`](R) reader structure"]
143impl crate::Readable for CE_ISR_SPEC {}
144#[doc = "`write(|w| ..)` method takes [`ce_isr::W`](W) writer structure"]
145impl crate::Writable for CE_ISR_SPEC {
146    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
147    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0f;
148}
149#[doc = "`reset()` method sets ce_isr to value 0"]
150impl crate::Resettable for CE_ISR_SPEC {
151    const RESET_VALUE: Self::Ux = 0;
152}
d1_pac/ce_ns/ce_isr.rs

d1_pac/ce_ns/
ce_isr.rs
