d1_pac/ccu/
ve_clk.rs

1#[doc = "Register `ve_clk` reader"]
2pub type R = crate::R<VE_CLK_SPEC>;
3#[doc = "Register `ve_clk` writer"]
4pub type W = crate::W<VE_CLK_SPEC>;
5#[doc = "Field `factor_m` reader - Factor M"]
6pub type FACTOR_M_R = crate::FieldReader;
7#[doc = "Field `factor_m` writer - Factor M"]
8pub type FACTOR_M_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
10pub type CLK_SRC_SEL_R = crate::BitReader<CLK_SRC_SEL_A>;
11#[doc = "Clock Source Select\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum CLK_SRC_SEL_A {
14    #[doc = "0: `0`"]
15    VEPLL = 0,
16    #[doc = "1: `1`"]
17    PLL_PERI_2X = 1,
18}
19impl From<CLK_SRC_SEL_A> for bool {
20    #[inline(always)]
21    fn from(variant: CLK_SRC_SEL_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl CLK_SRC_SEL_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> CLK_SRC_SEL_A {
29        match self.bits {
30            false => CLK_SRC_SEL_A::VEPLL,
31            true => CLK_SRC_SEL_A::PLL_PERI_2X,
32        }
33    }
34    #[doc = "`0`"]
35    #[inline(always)]
36    pub fn is_vepll(&self) -> bool {
37        *self == CLK_SRC_SEL_A::VEPLL
38    }
39    #[doc = "`1`"]
40    #[inline(always)]
41    pub fn is_pll_peri_2x(&self) -> bool {
42        *self == CLK_SRC_SEL_A::PLL_PERI_2X
43    }
44}
45#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
46pub type CLK_SRC_SEL_W<'a, REG> = crate::BitWriter<'a, REG, CLK_SRC_SEL_A>;
47impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "`0`"]
52    #[inline(always)]
53    pub fn vepll(self) -> &'a mut crate::W<REG> {
54        self.variant(CLK_SRC_SEL_A::VEPLL)
55    }
56    #[doc = "`1`"]
57    #[inline(always)]
58    pub fn pll_peri_2x(self) -> &'a mut crate::W<REG> {
59        self.variant(CLK_SRC_SEL_A::PLL_PERI_2X)
60    }
61}
62#[doc = "Field `clk_gating` reader - Gating Clock"]
63pub type CLK_GATING_R = crate::BitReader<CLK_GATING_A>;
64#[doc = "Gating Clock\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CLK_GATING_A {
67    #[doc = "0: `0`"]
68    OFF = 0,
69    #[doc = "1: `1`"]
70    ON = 1,
71}
72impl From<CLK_GATING_A> for bool {
73    #[inline(always)]
74    fn from(variant: CLK_GATING_A) -> Self {
75        variant as u8 != 0
76    }
77}
78impl CLK_GATING_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub const fn variant(&self) -> CLK_GATING_A {
82        match self.bits {
83            false => CLK_GATING_A::OFF,
84            true => CLK_GATING_A::ON,
85        }
86    }
87    #[doc = "`0`"]
88    #[inline(always)]
89    pub fn is_off(&self) -> bool {
90        *self == CLK_GATING_A::OFF
91    }
92    #[doc = "`1`"]
93    #[inline(always)]
94    pub fn is_on(&self) -> bool {
95        *self == CLK_GATING_A::ON
96    }
97}
98#[doc = "Field `clk_gating` writer - Gating Clock"]
99pub type CLK_GATING_W<'a, REG> = crate::BitWriter<'a, REG, CLK_GATING_A>;
100impl<'a, REG> CLK_GATING_W<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103{
104    #[doc = "`0`"]
105    #[inline(always)]
106    pub fn off(self) -> &'a mut crate::W<REG> {
107        self.variant(CLK_GATING_A::OFF)
108    }
109    #[doc = "`1`"]
110    #[inline(always)]
111    pub fn on(self) -> &'a mut crate::W<REG> {
112        self.variant(CLK_GATING_A::ON)
113    }
114}
115impl R {
116    #[doc = "Bits 0:4 - Factor M"]
117    #[inline(always)]
118    pub fn factor_m(&self) -> FACTOR_M_R {
119        FACTOR_M_R::new((self.bits & 0x1f) as u8)
120    }
121    #[doc = "Bit 24 - Clock Source Select"]
122    #[inline(always)]
123    pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
124        CLK_SRC_SEL_R::new(((self.bits >> 24) & 1) != 0)
125    }
126    #[doc = "Bit 31 - Gating Clock"]
127    #[inline(always)]
128    pub fn clk_gating(&self) -> CLK_GATING_R {
129        CLK_GATING_R::new(((self.bits >> 31) & 1) != 0)
130    }
131}
132impl W {
133    #[doc = "Bits 0:4 - Factor M"]
134    #[inline(always)]
135    #[must_use]
136    pub fn factor_m(&mut self) -> FACTOR_M_W<VE_CLK_SPEC> {
137        FACTOR_M_W::new(self, 0)
138    }
139    #[doc = "Bit 24 - Clock Source Select"]
140    #[inline(always)]
141    #[must_use]
142    pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<VE_CLK_SPEC> {
143        CLK_SRC_SEL_W::new(self, 24)
144    }
145    #[doc = "Bit 31 - Gating Clock"]
146    #[inline(always)]
147    #[must_use]
148    pub fn clk_gating(&mut self) -> CLK_GATING_W<VE_CLK_SPEC> {
149        CLK_GATING_W::new(self, 31)
150    }
151    #[doc = r" Writes raw bits to the register."]
152    #[doc = r""]
153    #[doc = r" # Safety"]
154    #[doc = r""]
155    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
156    #[inline(always)]
157    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
158        self.bits = bits;
159        self
160    }
161}
162#[doc = "VE Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ve_clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ve_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
163pub struct VE_CLK_SPEC;
164impl crate::RegisterSpec for VE_CLK_SPEC {
165    type Ux = u32;
166}
167#[doc = "`read()` method returns [`ve_clk::R`](R) reader structure"]
168impl crate::Readable for VE_CLK_SPEC {}
169#[doc = "`write(|w| ..)` method takes [`ve_clk::W`](W) writer structure"]
170impl crate::Writable for VE_CLK_SPEC {
171    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
172    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
173}
174#[doc = "`reset()` method sets ve_clk to value 0"]
175impl crate::Resettable for VE_CLK_SPEC {
176    const RESET_VALUE: Self::Ux = 0;
177}
d1_pac/ccu/ve_clk.rs

d1_pac/ccu/
ve_clk.rs
