d1_pac/ccu/
usb_bgr.rs

1#[doc = "Register `usb_bgr` reader"]
2pub type R = crate::R<USB_BGR_SPEC>;
3#[doc = "Register `usb_bgr` writer"]
4pub type W = crate::W<USB_BGR_SPEC>;
5#[doc = "Field `usbohci_gating[0-1]` reader - USBOHCI Gating Clock"]
6pub type USBOHCI_GATING_R = crate::BitReader<USBOHCI_GATING_A>;
7#[doc = "USBOHCI Gating Clock\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum USBOHCI_GATING_A {
10    #[doc = "0: `0`"]
11    MASK = 0,
12    #[doc = "1: `1`"]
13    PASS = 1,
14}
15impl From<USBOHCI_GATING_A> for bool {
16    #[inline(always)]
17    fn from(variant: USBOHCI_GATING_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl USBOHCI_GATING_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> USBOHCI_GATING_A {
25        match self.bits {
26            false => USBOHCI_GATING_A::MASK,
27            true => USBOHCI_GATING_A::PASS,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_mask(&self) -> bool {
33        *self == USBOHCI_GATING_A::MASK
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_pass(&self) -> bool {
38        *self == USBOHCI_GATING_A::PASS
39    }
40}
41#[doc = "Field `usbohci_gating[0-1]` writer - USBOHCI Gating Clock"]
42pub type USBOHCI_GATING_W<'a, REG> = crate::BitWriter<'a, REG, USBOHCI_GATING_A>;
43impl<'a, REG> USBOHCI_GATING_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn mask(self) -> &'a mut crate::W<REG> {
50        self.variant(USBOHCI_GATING_A::MASK)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn pass(self) -> &'a mut crate::W<REG> {
55        self.variant(USBOHCI_GATING_A::PASS)
56    }
57}
58#[doc = "Field `usbehci_gating[0-1]` reader - USBEHCI Gating Clock"]
59pub type USBEHCI_GATING_R = crate::BitReader<USBEHCI_GATING_A>;
60#[doc = "USBEHCI Gating Clock\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum USBEHCI_GATING_A {
63    #[doc = "0: `0`"]
64    MASK = 0,
65    #[doc = "1: `1`"]
66    PASS = 1,
67}
68impl From<USBEHCI_GATING_A> for bool {
69    #[inline(always)]
70    fn from(variant: USBEHCI_GATING_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl USBEHCI_GATING_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> USBEHCI_GATING_A {
78        match self.bits {
79            false => USBEHCI_GATING_A::MASK,
80            true => USBEHCI_GATING_A::PASS,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_mask(&self) -> bool {
86        *self == USBEHCI_GATING_A::MASK
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_pass(&self) -> bool {
91        *self == USBEHCI_GATING_A::PASS
92    }
93}
94#[doc = "Field `usbehci_gating[0-1]` writer - USBEHCI Gating Clock"]
95pub type USBEHCI_GATING_W<'a, REG> = crate::BitWriter<'a, REG, USBEHCI_GATING_A>;
96impl<'a, REG> USBEHCI_GATING_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn mask(self) -> &'a mut crate::W<REG> {
103        self.variant(USBEHCI_GATING_A::MASK)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn pass(self) -> &'a mut crate::W<REG> {
108        self.variant(USBEHCI_GATING_A::PASS)
109    }
110}
111#[doc = "Field `usbotg0_gating` reader - USBOTG0 Gating Clock"]
112pub type USBOTG0_GATING_R = crate::BitReader<USBOTG0_GATING_A>;
113#[doc = "USBOTG0 Gating Clock\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum USBOTG0_GATING_A {
116    #[doc = "0: `0`"]
117    MASK = 0,
118    #[doc = "1: `1`"]
119    PASS = 1,
120}
121impl From<USBOTG0_GATING_A> for bool {
122    #[inline(always)]
123    fn from(variant: USBOTG0_GATING_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl USBOTG0_GATING_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> USBOTG0_GATING_A {
131        match self.bits {
132            false => USBOTG0_GATING_A::MASK,
133            true => USBOTG0_GATING_A::PASS,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_mask(&self) -> bool {
139        *self == USBOTG0_GATING_A::MASK
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_pass(&self) -> bool {
144        *self == USBOTG0_GATING_A::PASS
145    }
146}
147#[doc = "Field `usbotg0_gating` writer - USBOTG0 Gating Clock"]
148pub type USBOTG0_GATING_W<'a, REG> = crate::BitWriter<'a, REG, USBOTG0_GATING_A>;
149impl<'a, REG> USBOTG0_GATING_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn mask(self) -> &'a mut crate::W<REG> {
156        self.variant(USBOTG0_GATING_A::MASK)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn pass(self) -> &'a mut crate::W<REG> {
161        self.variant(USBOTG0_GATING_A::PASS)
162    }
163}
164#[doc = "Field `usbohci_rst[0-1]` reader - USBOHCI Reset"]
165pub type USBOHCI_RST_R = crate::BitReader<USBOHCI_RST_A>;
166#[doc = "USBOHCI Reset\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum USBOHCI_RST_A {
169    #[doc = "0: `0`"]
170    ASSERT = 0,
171    #[doc = "1: `1`"]
172    DEASSERT = 1,
173}
174impl From<USBOHCI_RST_A> for bool {
175    #[inline(always)]
176    fn from(variant: USBOHCI_RST_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl USBOHCI_RST_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> USBOHCI_RST_A {
184        match self.bits {
185            false => USBOHCI_RST_A::ASSERT,
186            true => USBOHCI_RST_A::DEASSERT,
187        }
188    }
189    #[doc = "`0`"]
190    #[inline(always)]
191    pub fn is_assert(&self) -> bool {
192        *self == USBOHCI_RST_A::ASSERT
193    }
194    #[doc = "`1`"]
195    #[inline(always)]
196    pub fn is_deassert(&self) -> bool {
197        *self == USBOHCI_RST_A::DEASSERT
198    }
199}
200#[doc = "Field `usbohci_rst[0-1]` writer - USBOHCI Reset"]
201pub type USBOHCI_RST_W<'a, REG> = crate::BitWriter<'a, REG, USBOHCI_RST_A>;
202impl<'a, REG> USBOHCI_RST_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "`0`"]
207    #[inline(always)]
208    pub fn assert(self) -> &'a mut crate::W<REG> {
209        self.variant(USBOHCI_RST_A::ASSERT)
210    }
211    #[doc = "`1`"]
212    #[inline(always)]
213    pub fn deassert(self) -> &'a mut crate::W<REG> {
214        self.variant(USBOHCI_RST_A::DEASSERT)
215    }
216}
217#[doc = "Field `usbehci_rst[0-1]` reader - USBEHCI Reset"]
218pub type USBEHCI_RST_R = crate::BitReader<USBEHCI_RST_A>;
219#[doc = "USBEHCI Reset\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221pub enum USBEHCI_RST_A {
222    #[doc = "0: `0`"]
223    ASSERT = 0,
224    #[doc = "1: `1`"]
225    DEASSERT = 1,
226}
227impl From<USBEHCI_RST_A> for bool {
228    #[inline(always)]
229    fn from(variant: USBEHCI_RST_A) -> Self {
230        variant as u8 != 0
231    }
232}
233impl USBEHCI_RST_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> USBEHCI_RST_A {
237        match self.bits {
238            false => USBEHCI_RST_A::ASSERT,
239            true => USBEHCI_RST_A::DEASSERT,
240        }
241    }
242    #[doc = "`0`"]
243    #[inline(always)]
244    pub fn is_assert(&self) -> bool {
245        *self == USBEHCI_RST_A::ASSERT
246    }
247    #[doc = "`1`"]
248    #[inline(always)]
249    pub fn is_deassert(&self) -> bool {
250        *self == USBEHCI_RST_A::DEASSERT
251    }
252}
253#[doc = "Field `usbehci_rst[0-1]` writer - USBEHCI Reset"]
254pub type USBEHCI_RST_W<'a, REG> = crate::BitWriter<'a, REG, USBEHCI_RST_A>;
255impl<'a, REG> USBEHCI_RST_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "`0`"]
260    #[inline(always)]
261    pub fn assert(self) -> &'a mut crate::W<REG> {
262        self.variant(USBEHCI_RST_A::ASSERT)
263    }
264    #[doc = "`1`"]
265    #[inline(always)]
266    pub fn deassert(self) -> &'a mut crate::W<REG> {
267        self.variant(USBEHCI_RST_A::DEASSERT)
268    }
269}
270#[doc = "Field `usbotg0_rst` reader - USBOTG0 Reset"]
271pub type USBOTG0_RST_R = crate::BitReader<USBOTG0_RST_A>;
272#[doc = "USBOTG0 Reset\n\nValue on reset: 0"]
273#[derive(Clone, Copy, Debug, PartialEq, Eq)]
274pub enum USBOTG0_RST_A {
275    #[doc = "0: `0`"]
276    ASSERT = 0,
277    #[doc = "1: `1`"]
278    DEASSERT = 1,
279}
280impl From<USBOTG0_RST_A> for bool {
281    #[inline(always)]
282    fn from(variant: USBOTG0_RST_A) -> Self {
283        variant as u8 != 0
284    }
285}
286impl USBOTG0_RST_R {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> USBOTG0_RST_A {
290        match self.bits {
291            false => USBOTG0_RST_A::ASSERT,
292            true => USBOTG0_RST_A::DEASSERT,
293        }
294    }
295    #[doc = "`0`"]
296    #[inline(always)]
297    pub fn is_assert(&self) -> bool {
298        *self == USBOTG0_RST_A::ASSERT
299    }
300    #[doc = "`1`"]
301    #[inline(always)]
302    pub fn is_deassert(&self) -> bool {
303        *self == USBOTG0_RST_A::DEASSERT
304    }
305}
306#[doc = "Field `usbotg0_rst` writer - USBOTG0 Reset"]
307pub type USBOTG0_RST_W<'a, REG> = crate::BitWriter<'a, REG, USBOTG0_RST_A>;
308impl<'a, REG> USBOTG0_RST_W<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "`0`"]
313    #[inline(always)]
314    pub fn assert(self) -> &'a mut crate::W<REG> {
315        self.variant(USBOTG0_RST_A::ASSERT)
316    }
317    #[doc = "`1`"]
318    #[inline(always)]
319    pub fn deassert(self) -> &'a mut crate::W<REG> {
320        self.variant(USBOTG0_RST_A::DEASSERT)
321    }
322}
323impl R {
324    #[doc = "USBOHCI Gating Clock\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `usbohci0_gating` field"]
325    #[inline(always)]
326    pub fn usbohci_gating(&self, n: u8) -> USBOHCI_GATING_R {
327        #[allow(clippy::no_effect)]
328        [(); 2][n as usize];
329        USBOHCI_GATING_R::new(((self.bits >> n) & 1) != 0)
330    }
331    #[doc = "Bit 0 - USBOHCI Gating Clock"]
332    #[inline(always)]
333    pub fn usbohci0_gating(&self) -> USBOHCI_GATING_R {
334        USBOHCI_GATING_R::new((self.bits & 1) != 0)
335    }
336    #[doc = "Bit 1 - USBOHCI Gating Clock"]
337    #[inline(always)]
338    pub fn usbohci1_gating(&self) -> USBOHCI_GATING_R {
339        USBOHCI_GATING_R::new(((self.bits >> 1) & 1) != 0)
340    }
341    #[doc = "USBEHCI Gating Clock\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `usbehci0_gating` field"]
342    #[inline(always)]
343    pub fn usbehci_gating(&self, n: u8) -> USBEHCI_GATING_R {
344        #[allow(clippy::no_effect)]
345        [(); 2][n as usize];
346        USBEHCI_GATING_R::new(((self.bits >> (n + 4)) & 1) != 0)
347    }
348    #[doc = "Bit 4 - USBEHCI Gating Clock"]
349    #[inline(always)]
350    pub fn usbehci0_gating(&self) -> USBEHCI_GATING_R {
351        USBEHCI_GATING_R::new(((self.bits >> 4) & 1) != 0)
352    }
353    #[doc = "Bit 5 - USBEHCI Gating Clock"]
354    #[inline(always)]
355    pub fn usbehci1_gating(&self) -> USBEHCI_GATING_R {
356        USBEHCI_GATING_R::new(((self.bits >> 5) & 1) != 0)
357    }
358    #[doc = "Bit 8 - USBOTG0 Gating Clock"]
359    #[inline(always)]
360    pub fn usbotg0_gating(&self) -> USBOTG0_GATING_R {
361        USBOTG0_GATING_R::new(((self.bits >> 8) & 1) != 0)
362    }
363    #[doc = "USBOHCI Reset\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `usbohci0_rst` field"]
364    #[inline(always)]
365    pub fn usbohci_rst(&self, n: u8) -> USBOHCI_RST_R {
366        #[allow(clippy::no_effect)]
367        [(); 2][n as usize];
368        USBOHCI_RST_R::new(((self.bits >> (n + 16)) & 1) != 0)
369    }
370    #[doc = "Bit 16 - USBOHCI Reset"]
371    #[inline(always)]
372    pub fn usbohci0_rst(&self) -> USBOHCI_RST_R {
373        USBOHCI_RST_R::new(((self.bits >> 16) & 1) != 0)
374    }
375    #[doc = "Bit 17 - USBOHCI Reset"]
376    #[inline(always)]
377    pub fn usbohci1_rst(&self) -> USBOHCI_RST_R {
378        USBOHCI_RST_R::new(((self.bits >> 17) & 1) != 0)
379    }
380    #[doc = "USBEHCI Reset\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `usbehci0_rst` field"]
381    #[inline(always)]
382    pub fn usbehci_rst(&self, n: u8) -> USBEHCI_RST_R {
383        #[allow(clippy::no_effect)]
384        [(); 2][n as usize];
385        USBEHCI_RST_R::new(((self.bits >> (n + 20)) & 1) != 0)
386    }
387    #[doc = "Bit 20 - USBEHCI Reset"]
388    #[inline(always)]
389    pub fn usbehci0_rst(&self) -> USBEHCI_RST_R {
390        USBEHCI_RST_R::new(((self.bits >> 20) & 1) != 0)
391    }
392    #[doc = "Bit 21 - USBEHCI Reset"]
393    #[inline(always)]
394    pub fn usbehci1_rst(&self) -> USBEHCI_RST_R {
395        USBEHCI_RST_R::new(((self.bits >> 21) & 1) != 0)
396    }
397    #[doc = "Bit 24 - USBOTG0 Reset"]
398    #[inline(always)]
399    pub fn usbotg0_rst(&self) -> USBOTG0_RST_R {
400        USBOTG0_RST_R::new(((self.bits >> 24) & 1) != 0)
401    }
402}
403impl W {
404    #[doc = "USBOHCI Gating Clock\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `usbohci0_gating` field"]
405    #[inline(always)]
406    #[must_use]
407    pub fn usbohci_gating(&mut self, n: u8) -> USBOHCI_GATING_W<USB_BGR_SPEC> {
408        #[allow(clippy::no_effect)]
409        [(); 2][n as usize];
410        USBOHCI_GATING_W::new(self, n)
411    }
412    #[doc = "Bit 0 - USBOHCI Gating Clock"]
413    #[inline(always)]
414    #[must_use]
415    pub fn usbohci0_gating(&mut self) -> USBOHCI_GATING_W<USB_BGR_SPEC> {
416        USBOHCI_GATING_W::new(self, 0)
417    }
418    #[doc = "Bit 1 - USBOHCI Gating Clock"]
419    #[inline(always)]
420    #[must_use]
421    pub fn usbohci1_gating(&mut self) -> USBOHCI_GATING_W<USB_BGR_SPEC> {
422        USBOHCI_GATING_W::new(self, 1)
423    }
424    #[doc = "USBEHCI Gating Clock\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `usbehci0_gating` field"]
425    #[inline(always)]
426    #[must_use]
427    pub fn usbehci_gating(&mut self, n: u8) -> USBEHCI_GATING_W<USB_BGR_SPEC> {
428        #[allow(clippy::no_effect)]
429        [(); 2][n as usize];
430        USBEHCI_GATING_W::new(self, n + 4)
431    }
432    #[doc = "Bit 4 - USBEHCI Gating Clock"]
433    #[inline(always)]
434    #[must_use]
435    pub fn usbehci0_gating(&mut self) -> USBEHCI_GATING_W<USB_BGR_SPEC> {
436        USBEHCI_GATING_W::new(self, 4)
437    }
438    #[doc = "Bit 5 - USBEHCI Gating Clock"]
439    #[inline(always)]
440    #[must_use]
441    pub fn usbehci1_gating(&mut self) -> USBEHCI_GATING_W<USB_BGR_SPEC> {
442        USBEHCI_GATING_W::new(self, 5)
443    }
444    #[doc = "Bit 8 - USBOTG0 Gating Clock"]
445    #[inline(always)]
446    #[must_use]
447    pub fn usbotg0_gating(&mut self) -> USBOTG0_GATING_W<USB_BGR_SPEC> {
448        USBOTG0_GATING_W::new(self, 8)
449    }
450    #[doc = "USBOHCI Reset\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `usbohci0_rst` field"]
451    #[inline(always)]
452    #[must_use]
453    pub fn usbohci_rst(&mut self, n: u8) -> USBOHCI_RST_W<USB_BGR_SPEC> {
454        #[allow(clippy::no_effect)]
455        [(); 2][n as usize];
456        USBOHCI_RST_W::new(self, n + 16)
457    }
458    #[doc = "Bit 16 - USBOHCI Reset"]
459    #[inline(always)]
460    #[must_use]
461    pub fn usbohci0_rst(&mut self) -> USBOHCI_RST_W<USB_BGR_SPEC> {
462        USBOHCI_RST_W::new(self, 16)
463    }
464    #[doc = "Bit 17 - USBOHCI Reset"]
465    #[inline(always)]
466    #[must_use]
467    pub fn usbohci1_rst(&mut self) -> USBOHCI_RST_W<USB_BGR_SPEC> {
468        USBOHCI_RST_W::new(self, 17)
469    }
470    #[doc = "USBEHCI Reset\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `usbehci0_rst` field"]
471    #[inline(always)]
472    #[must_use]
473    pub fn usbehci_rst(&mut self, n: u8) -> USBEHCI_RST_W<USB_BGR_SPEC> {
474        #[allow(clippy::no_effect)]
475        [(); 2][n as usize];
476        USBEHCI_RST_W::new(self, n + 20)
477    }
478    #[doc = "Bit 20 - USBEHCI Reset"]
479    #[inline(always)]
480    #[must_use]
481    pub fn usbehci0_rst(&mut self) -> USBEHCI_RST_W<USB_BGR_SPEC> {
482        USBEHCI_RST_W::new(self, 20)
483    }
484    #[doc = "Bit 21 - USBEHCI Reset"]
485    #[inline(always)]
486    #[must_use]
487    pub fn usbehci1_rst(&mut self) -> USBEHCI_RST_W<USB_BGR_SPEC> {
488        USBEHCI_RST_W::new(self, 21)
489    }
490    #[doc = "Bit 24 - USBOTG0 Reset"]
491    #[inline(always)]
492    #[must_use]
493    pub fn usbotg0_rst(&mut self) -> USBOTG0_RST_W<USB_BGR_SPEC> {
494        USBOTG0_RST_W::new(self, 24)
495    }
496    #[doc = r" Writes raw bits to the register."]
497    #[doc = r""]
498    #[doc = r" # Safety"]
499    #[doc = r""]
500    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
501    #[inline(always)]
502    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
503        self.bits = bits;
504        self
505    }
506}
507#[doc = "USB Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_bgr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_bgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
508pub struct USB_BGR_SPEC;
509impl crate::RegisterSpec for USB_BGR_SPEC {
510    type Ux = u32;
511}
512#[doc = "`read()` method returns [`usb_bgr::R`](R) reader structure"]
513impl crate::Readable for USB_BGR_SPEC {}
514#[doc = "`write(|w| ..)` method takes [`usb_bgr::W`](W) writer structure"]
515impl crate::Writable for USB_BGR_SPEC {
516    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
517    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
518}
519#[doc = "`reset()` method sets usb_bgr to value 0"]
520impl crate::Resettable for USB_BGR_SPEC {
521    const RESET_VALUE: Self::Ux = 0;
522}
d1_pac/ccu/usb_bgr.rs

d1_pac/ccu/
usb_bgr.rs
