d1_pac/ccu/
uart_bgr.rs

1#[doc = "Register `uart_bgr` reader"]
2pub type R = crate::R<UART_BGR_SPEC>;
3#[doc = "Register `uart_bgr` writer"]
4pub type W = crate::W<UART_BGR_SPEC>;
5#[doc = "Field `uart_gating[0-5]` reader - Gating Clock"]
6pub type UART_GATING_R = crate::BitReader<UART_GATING_A>;
7#[doc = "Gating Clock\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum UART_GATING_A {
10    #[doc = "0: `0`"]
11    MASK = 0,
12    #[doc = "1: `1`"]
13    PASS = 1,
14}
15impl From<UART_GATING_A> for bool {
16    #[inline(always)]
17    fn from(variant: UART_GATING_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl UART_GATING_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> UART_GATING_A {
25        match self.bits {
26            false => UART_GATING_A::MASK,
27            true => UART_GATING_A::PASS,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_mask(&self) -> bool {
33        *self == UART_GATING_A::MASK
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_pass(&self) -> bool {
38        *self == UART_GATING_A::PASS
39    }
40}
41#[doc = "Field `uart_gating[0-5]` writer - Gating Clock"]
42pub type UART_GATING_W<'a, REG> = crate::BitWriter<'a, REG, UART_GATING_A>;
43impl<'a, REG> UART_GATING_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn mask(self) -> &'a mut crate::W<REG> {
50        self.variant(UART_GATING_A::MASK)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn pass(self) -> &'a mut crate::W<REG> {
55        self.variant(UART_GATING_A::PASS)
56    }
57}
58#[doc = "Field `uart_rst[0-5]` reader - Reset"]
59pub type UART_RST_R = crate::BitReader<UART_RST_A>;
60#[doc = "Reset\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum UART_RST_A {
63    #[doc = "0: `0`"]
64    ASSERT = 0,
65    #[doc = "1: `1`"]
66    DEASSERT = 1,
67}
68impl From<UART_RST_A> for bool {
69    #[inline(always)]
70    fn from(variant: UART_RST_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl UART_RST_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> UART_RST_A {
78        match self.bits {
79            false => UART_RST_A::ASSERT,
80            true => UART_RST_A::DEASSERT,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_assert(&self) -> bool {
86        *self == UART_RST_A::ASSERT
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_deassert(&self) -> bool {
91        *self == UART_RST_A::DEASSERT
92    }
93}
94#[doc = "Field `uart_rst[0-5]` writer - Reset"]
95pub type UART_RST_W<'a, REG> = crate::BitWriter<'a, REG, UART_RST_A>;
96impl<'a, REG> UART_RST_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn assert(self) -> &'a mut crate::W<REG> {
103        self.variant(UART_RST_A::ASSERT)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn deassert(self) -> &'a mut crate::W<REG> {
108        self.variant(UART_RST_A::DEASSERT)
109    }
110}
111impl R {
112    #[doc = "Gating Clock\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `uart0_gating` field"]
113    #[inline(always)]
114    pub fn uart_gating(&self, n: u8) -> UART_GATING_R {
115        #[allow(clippy::no_effect)]
116        [(); 6][n as usize];
117        UART_GATING_R::new(((self.bits >> n) & 1) != 0)
118    }
119    #[doc = "Bit 0 - Gating Clock"]
120    #[inline(always)]
121    pub fn uart0_gating(&self) -> UART_GATING_R {
122        UART_GATING_R::new((self.bits & 1) != 0)
123    }
124    #[doc = "Bit 1 - Gating Clock"]
125    #[inline(always)]
126    pub fn uart1_gating(&self) -> UART_GATING_R {
127        UART_GATING_R::new(((self.bits >> 1) & 1) != 0)
128    }
129    #[doc = "Bit 2 - Gating Clock"]
130    #[inline(always)]
131    pub fn uart2_gating(&self) -> UART_GATING_R {
132        UART_GATING_R::new(((self.bits >> 2) & 1) != 0)
133    }
134    #[doc = "Bit 3 - Gating Clock"]
135    #[inline(always)]
136    pub fn uart3_gating(&self) -> UART_GATING_R {
137        UART_GATING_R::new(((self.bits >> 3) & 1) != 0)
138    }
139    #[doc = "Bit 4 - Gating Clock"]
140    #[inline(always)]
141    pub fn uart4_gating(&self) -> UART_GATING_R {
142        UART_GATING_R::new(((self.bits >> 4) & 1) != 0)
143    }
144    #[doc = "Bit 5 - Gating Clock"]
145    #[inline(always)]
146    pub fn uart5_gating(&self) -> UART_GATING_R {
147        UART_GATING_R::new(((self.bits >> 5) & 1) != 0)
148    }
149    #[doc = "Reset\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `uart0_rst` field"]
150    #[inline(always)]
151    pub fn uart_rst(&self, n: u8) -> UART_RST_R {
152        #[allow(clippy::no_effect)]
153        [(); 6][n as usize];
154        UART_RST_R::new(((self.bits >> (n + 16)) & 1) != 0)
155    }
156    #[doc = "Bit 16 - Reset"]
157    #[inline(always)]
158    pub fn uart0_rst(&self) -> UART_RST_R {
159        UART_RST_R::new(((self.bits >> 16) & 1) != 0)
160    }
161    #[doc = "Bit 17 - Reset"]
162    #[inline(always)]
163    pub fn uart1_rst(&self) -> UART_RST_R {
164        UART_RST_R::new(((self.bits >> 17) & 1) != 0)
165    }
166    #[doc = "Bit 18 - Reset"]
167    #[inline(always)]
168    pub fn uart2_rst(&self) -> UART_RST_R {
169        UART_RST_R::new(((self.bits >> 18) & 1) != 0)
170    }
171    #[doc = "Bit 19 - Reset"]
172    #[inline(always)]
173    pub fn uart3_rst(&self) -> UART_RST_R {
174        UART_RST_R::new(((self.bits >> 19) & 1) != 0)
175    }
176    #[doc = "Bit 20 - Reset"]
177    #[inline(always)]
178    pub fn uart4_rst(&self) -> UART_RST_R {
179        UART_RST_R::new(((self.bits >> 20) & 1) != 0)
180    }
181    #[doc = "Bit 21 - Reset"]
182    #[inline(always)]
183    pub fn uart5_rst(&self) -> UART_RST_R {
184        UART_RST_R::new(((self.bits >> 21) & 1) != 0)
185    }
186}
187impl W {
188    #[doc = "Gating Clock\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `uart0_gating` field"]
189    #[inline(always)]
190    #[must_use]
191    pub fn uart_gating(&mut self, n: u8) -> UART_GATING_W<UART_BGR_SPEC> {
192        #[allow(clippy::no_effect)]
193        [(); 6][n as usize];
194        UART_GATING_W::new(self, n)
195    }
196    #[doc = "Bit 0 - Gating Clock"]
197    #[inline(always)]
198    #[must_use]
199    pub fn uart0_gating(&mut self) -> UART_GATING_W<UART_BGR_SPEC> {
200        UART_GATING_W::new(self, 0)
201    }
202    #[doc = "Bit 1 - Gating Clock"]
203    #[inline(always)]
204    #[must_use]
205    pub fn uart1_gating(&mut self) -> UART_GATING_W<UART_BGR_SPEC> {
206        UART_GATING_W::new(self, 1)
207    }
208    #[doc = "Bit 2 - Gating Clock"]
209    #[inline(always)]
210    #[must_use]
211    pub fn uart2_gating(&mut self) -> UART_GATING_W<UART_BGR_SPEC> {
212        UART_GATING_W::new(self, 2)
213    }
214    #[doc = "Bit 3 - Gating Clock"]
215    #[inline(always)]
216    #[must_use]
217    pub fn uart3_gating(&mut self) -> UART_GATING_W<UART_BGR_SPEC> {
218        UART_GATING_W::new(self, 3)
219    }
220    #[doc = "Bit 4 - Gating Clock"]
221    #[inline(always)]
222    #[must_use]
223    pub fn uart4_gating(&mut self) -> UART_GATING_W<UART_BGR_SPEC> {
224        UART_GATING_W::new(self, 4)
225    }
226    #[doc = "Bit 5 - Gating Clock"]
227    #[inline(always)]
228    #[must_use]
229    pub fn uart5_gating(&mut self) -> UART_GATING_W<UART_BGR_SPEC> {
230        UART_GATING_W::new(self, 5)
231    }
232    #[doc = "Reset\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `uart0_rst` field"]
233    #[inline(always)]
234    #[must_use]
235    pub fn uart_rst(&mut self, n: u8) -> UART_RST_W<UART_BGR_SPEC> {
236        #[allow(clippy::no_effect)]
237        [(); 6][n as usize];
238        UART_RST_W::new(self, n + 16)
239    }
240    #[doc = "Bit 16 - Reset"]
241    #[inline(always)]
242    #[must_use]
243    pub fn uart0_rst(&mut self) -> UART_RST_W<UART_BGR_SPEC> {
244        UART_RST_W::new(self, 16)
245    }
246    #[doc = "Bit 17 - Reset"]
247    #[inline(always)]
248    #[must_use]
249    pub fn uart1_rst(&mut self) -> UART_RST_W<UART_BGR_SPEC> {
250        UART_RST_W::new(self, 17)
251    }
252    #[doc = "Bit 18 - Reset"]
253    #[inline(always)]
254    #[must_use]
255    pub fn uart2_rst(&mut self) -> UART_RST_W<UART_BGR_SPEC> {
256        UART_RST_W::new(self, 18)
257    }
258    #[doc = "Bit 19 - Reset"]
259    #[inline(always)]
260    #[must_use]
261    pub fn uart3_rst(&mut self) -> UART_RST_W<UART_BGR_SPEC> {
262        UART_RST_W::new(self, 19)
263    }
264    #[doc = "Bit 20 - Reset"]
265    #[inline(always)]
266    #[must_use]
267    pub fn uart4_rst(&mut self) -> UART_RST_W<UART_BGR_SPEC> {
268        UART_RST_W::new(self, 20)
269    }
270    #[doc = "Bit 21 - Reset"]
271    #[inline(always)]
272    #[must_use]
273    pub fn uart5_rst(&mut self) -> UART_RST_W<UART_BGR_SPEC> {
274        UART_RST_W::new(self, 21)
275    }
276    #[doc = r" Writes raw bits to the register."]
277    #[doc = r""]
278    #[doc = r" # Safety"]
279    #[doc = r""]
280    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
281    #[inline(always)]
282    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
283        self.bits = bits;
284        self
285    }
286}
287#[doc = "UART Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_bgr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_bgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
288pub struct UART_BGR_SPEC;
289impl crate::RegisterSpec for UART_BGR_SPEC {
290    type Ux = u32;
291}
292#[doc = "`read()` method returns [`uart_bgr::R`](R) reader structure"]
293impl crate::Readable for UART_BGR_SPEC {}
294#[doc = "`write(|w| ..)` method takes [`uart_bgr::W`](W) writer structure"]
295impl crate::Writable for UART_BGR_SPEC {
296    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
297    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
298}
299#[doc = "`reset()` method sets uart_bgr to value 0"]
300impl crate::Resettable for UART_BGR_SPEC {
301    const RESET_VALUE: Self::Ux = 0;
302}
d1_pac/ccu/uart_bgr.rs

d1_pac/ccu/
uart_bgr.rs
