1#[doc = "Register `twi_bgr` reader"]
2pub type R = crate::R<TWI_BGR_SPEC>;
3#[doc = "Register `twi_bgr` writer"]
4pub type W = crate::W<TWI_BGR_SPEC>;
5#[doc = "Field `twi_gating[0-3]` reader - Gating Clock"]
6pub type TWI_GATING_R = crate::BitReader<TWI_GATING_A>;
7#[doc = "Gating Clock\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TWI_GATING_A {
10 #[doc = "0: `0`"]
11 MASK = 0,
12 #[doc = "1: `1`"]
13 PASS = 1,
14}
15impl From<TWI_GATING_A> for bool {
16 #[inline(always)]
17 fn from(variant: TWI_GATING_A) -> Self {
18 variant as u8 != 0
19 }
20}
21impl TWI_GATING_R {
22 #[doc = "Get enumerated values variant"]
23 #[inline(always)]
24 pub const fn variant(&self) -> TWI_GATING_A {
25 match self.bits {
26 false => TWI_GATING_A::MASK,
27 true => TWI_GATING_A::PASS,
28 }
29 }
30 #[doc = "`0`"]
31 #[inline(always)]
32 pub fn is_mask(&self) -> bool {
33 *self == TWI_GATING_A::MASK
34 }
35 #[doc = "`1`"]
36 #[inline(always)]
37 pub fn is_pass(&self) -> bool {
38 *self == TWI_GATING_A::PASS
39 }
40}
41#[doc = "Field `twi_gating[0-3]` writer - Gating Clock"]
42pub type TWI_GATING_W<'a, REG> = crate::BitWriter<'a, REG, TWI_GATING_A>;
43impl<'a, REG> TWI_GATING_W<'a, REG>
44where
45 REG: crate::Writable + crate::RegisterSpec,
46{
47 #[doc = "`0`"]
48 #[inline(always)]
49 pub fn mask(self) -> &'a mut crate::W<REG> {
50 self.variant(TWI_GATING_A::MASK)
51 }
52 #[doc = "`1`"]
53 #[inline(always)]
54 pub fn pass(self) -> &'a mut crate::W<REG> {
55 self.variant(TWI_GATING_A::PASS)
56 }
57}
58#[doc = "Field `twi_rst[0-3]` reader - Reset"]
59pub type TWI_RST_R = crate::BitReader<TWI_RST_A>;
60#[doc = "Reset\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum TWI_RST_A {
63 #[doc = "0: `0`"]
64 ASSERT = 0,
65 #[doc = "1: `1`"]
66 DEASSERT = 1,
67}
68impl From<TWI_RST_A> for bool {
69 #[inline(always)]
70 fn from(variant: TWI_RST_A) -> Self {
71 variant as u8 != 0
72 }
73}
74impl TWI_RST_R {
75 #[doc = "Get enumerated values variant"]
76 #[inline(always)]
77 pub const fn variant(&self) -> TWI_RST_A {
78 match self.bits {
79 false => TWI_RST_A::ASSERT,
80 true => TWI_RST_A::DEASSERT,
81 }
82 }
83 #[doc = "`0`"]
84 #[inline(always)]
85 pub fn is_assert(&self) -> bool {
86 *self == TWI_RST_A::ASSERT
87 }
88 #[doc = "`1`"]
89 #[inline(always)]
90 pub fn is_deassert(&self) -> bool {
91 *self == TWI_RST_A::DEASSERT
92 }
93}
94#[doc = "Field `twi_rst[0-3]` writer - Reset"]
95pub type TWI_RST_W<'a, REG> = crate::BitWriter<'a, REG, TWI_RST_A>;
96impl<'a, REG> TWI_RST_W<'a, REG>
97where
98 REG: crate::Writable + crate::RegisterSpec,
99{
100 #[doc = "`0`"]
101 #[inline(always)]
102 pub fn assert(self) -> &'a mut crate::W<REG> {
103 self.variant(TWI_RST_A::ASSERT)
104 }
105 #[doc = "`1`"]
106 #[inline(always)]
107 pub fn deassert(self) -> &'a mut crate::W<REG> {
108 self.variant(TWI_RST_A::DEASSERT)
109 }
110}
111impl R {
112 #[doc = "Gating Clock\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `twi0_gating` field"]
113 #[inline(always)]
114 pub fn twi_gating(&self, n: u8) -> TWI_GATING_R {
115 #[allow(clippy::no_effect)]
116 [(); 4][n as usize];
117 TWI_GATING_R::new(((self.bits >> n) & 1) != 0)
118 }
119 #[doc = "Bit 0 - Gating Clock"]
120 #[inline(always)]
121 pub fn twi0_gating(&self) -> TWI_GATING_R {
122 TWI_GATING_R::new((self.bits & 1) != 0)
123 }
124 #[doc = "Bit 1 - Gating Clock"]
125 #[inline(always)]
126 pub fn twi1_gating(&self) -> TWI_GATING_R {
127 TWI_GATING_R::new(((self.bits >> 1) & 1) != 0)
128 }
129 #[doc = "Bit 2 - Gating Clock"]
130 #[inline(always)]
131 pub fn twi2_gating(&self) -> TWI_GATING_R {
132 TWI_GATING_R::new(((self.bits >> 2) & 1) != 0)
133 }
134 #[doc = "Bit 3 - Gating Clock"]
135 #[inline(always)]
136 pub fn twi3_gating(&self) -> TWI_GATING_R {
137 TWI_GATING_R::new(((self.bits >> 3) & 1) != 0)
138 }
139 #[doc = "Reset\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `twi0_rst` field"]
140 #[inline(always)]
141 pub fn twi_rst(&self, n: u8) -> TWI_RST_R {
142 #[allow(clippy::no_effect)]
143 [(); 4][n as usize];
144 TWI_RST_R::new(((self.bits >> (n + 16)) & 1) != 0)
145 }
146 #[doc = "Bit 16 - Reset"]
147 #[inline(always)]
148 pub fn twi0_rst(&self) -> TWI_RST_R {
149 TWI_RST_R::new(((self.bits >> 16) & 1) != 0)
150 }
151 #[doc = "Bit 17 - Reset"]
152 #[inline(always)]
153 pub fn twi1_rst(&self) -> TWI_RST_R {
154 TWI_RST_R::new(((self.bits >> 17) & 1) != 0)
155 }
156 #[doc = "Bit 18 - Reset"]
157 #[inline(always)]
158 pub fn twi2_rst(&self) -> TWI_RST_R {
159 TWI_RST_R::new(((self.bits >> 18) & 1) != 0)
160 }
161 #[doc = "Bit 19 - Reset"]
162 #[inline(always)]
163 pub fn twi3_rst(&self) -> TWI_RST_R {
164 TWI_RST_R::new(((self.bits >> 19) & 1) != 0)
165 }
166}
167impl W {
168 #[doc = "Gating Clock\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `twi0_gating` field"]
169 #[inline(always)]
170 #[must_use]
171 pub fn twi_gating(&mut self, n: u8) -> TWI_GATING_W<TWI_BGR_SPEC> {
172 #[allow(clippy::no_effect)]
173 [(); 4][n as usize];
174 TWI_GATING_W::new(self, n)
175 }
176 #[doc = "Bit 0 - Gating Clock"]
177 #[inline(always)]
178 #[must_use]
179 pub fn twi0_gating(&mut self) -> TWI_GATING_W<TWI_BGR_SPEC> {
180 TWI_GATING_W::new(self, 0)
181 }
182 #[doc = "Bit 1 - Gating Clock"]
183 #[inline(always)]
184 #[must_use]
185 pub fn twi1_gating(&mut self) -> TWI_GATING_W<TWI_BGR_SPEC> {
186 TWI_GATING_W::new(self, 1)
187 }
188 #[doc = "Bit 2 - Gating Clock"]
189 #[inline(always)]
190 #[must_use]
191 pub fn twi2_gating(&mut self) -> TWI_GATING_W<TWI_BGR_SPEC> {
192 TWI_GATING_W::new(self, 2)
193 }
194 #[doc = "Bit 3 - Gating Clock"]
195 #[inline(always)]
196 #[must_use]
197 pub fn twi3_gating(&mut self) -> TWI_GATING_W<TWI_BGR_SPEC> {
198 TWI_GATING_W::new(self, 3)
199 }
200 #[doc = "Reset\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `twi0_rst` field"]
201 #[inline(always)]
202 #[must_use]
203 pub fn twi_rst(&mut self, n: u8) -> TWI_RST_W<TWI_BGR_SPEC> {
204 #[allow(clippy::no_effect)]
205 [(); 4][n as usize];
206 TWI_RST_W::new(self, n + 16)
207 }
208 #[doc = "Bit 16 - Reset"]
209 #[inline(always)]
210 #[must_use]
211 pub fn twi0_rst(&mut self) -> TWI_RST_W<TWI_BGR_SPEC> {
212 TWI_RST_W::new(self, 16)
213 }
214 #[doc = "Bit 17 - Reset"]
215 #[inline(always)]
216 #[must_use]
217 pub fn twi1_rst(&mut self) -> TWI_RST_W<TWI_BGR_SPEC> {
218 TWI_RST_W::new(self, 17)
219 }
220 #[doc = "Bit 18 - Reset"]
221 #[inline(always)]
222 #[must_use]
223 pub fn twi2_rst(&mut self) -> TWI_RST_W<TWI_BGR_SPEC> {
224 TWI_RST_W::new(self, 18)
225 }
226 #[doc = "Bit 19 - Reset"]
227 #[inline(always)]
228 #[must_use]
229 pub fn twi3_rst(&mut self) -> TWI_RST_W<TWI_BGR_SPEC> {
230 TWI_RST_W::new(self, 19)
231 }
232 #[doc = r" Writes raw bits to the register."]
233 #[doc = r""]
234 #[doc = r" # Safety"]
235 #[doc = r""]
236 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
237 #[inline(always)]
238 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
239 self.bits = bits;
240 self
241 }
242}
243#[doc = "TWI Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`twi_bgr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`twi_bgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
244pub struct TWI_BGR_SPEC;
245impl crate::RegisterSpec for TWI_BGR_SPEC {
246 type Ux = u32;
247}
248#[doc = "`read()` method returns [`twi_bgr::R`](R) reader structure"]
249impl crate::Readable for TWI_BGR_SPEC {}
250#[doc = "`write(|w| ..)` method takes [`twi_bgr::W`](W) writer structure"]
251impl crate::Writable for TWI_BGR_SPEC {
252 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
253 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
254}
255#[doc = "`reset()` method sets twi_bgr to value 0"]
256impl crate::Resettable for TWI_BGR_SPEC {
257 const RESET_VALUE: Self::Ux = 0;
258}