d1_pac/ccu/
tvd_clk.rs

1#[doc = "Register `tvd_clk` reader"]
2pub type R = crate::R<TVD_CLK_SPEC>;
3#[doc = "Register `tvd_clk` writer"]
4pub type W = crate::W<TVD_CLK_SPEC>;
5#[doc = "Field `factor_m` reader - Factor M"]
6pub type FACTOR_M_R = crate::FieldReader;
7#[doc = "Field `factor_m` writer - Factor M"]
8pub type FACTOR_M_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
10pub type CLK_SRC_SEL_R = crate::FieldReader<CLK_SRC_SEL_A>;
11#[doc = "Clock Source Select\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum CLK_SRC_SEL_A {
15    #[doc = "0: `0`"]
16    HOSC = 0,
17    #[doc = "1: `1`"]
18    PLL_VIDEO0_1X = 1,
19    #[doc = "2: `10`"]
20    PLL_VIDEO1_1X = 2,
21    #[doc = "3: `11`"]
22    PLL_PERI_1X = 3,
23}
24impl From<CLK_SRC_SEL_A> for u8 {
25    #[inline(always)]
26    fn from(variant: CLK_SRC_SEL_A) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for CLK_SRC_SEL_A {
31    type Ux = u8;
32}
33impl CLK_SRC_SEL_R {
34    #[doc = "Get enumerated values variant"]
35    #[inline(always)]
36    pub const fn variant(&self) -> Option<CLK_SRC_SEL_A> {
37        match self.bits {
38            0 => Some(CLK_SRC_SEL_A::HOSC),
39            1 => Some(CLK_SRC_SEL_A::PLL_VIDEO0_1X),
40            2 => Some(CLK_SRC_SEL_A::PLL_VIDEO1_1X),
41            3 => Some(CLK_SRC_SEL_A::PLL_PERI_1X),
42            _ => None,
43        }
44    }
45    #[doc = "`0`"]
46    #[inline(always)]
47    pub fn is_hosc(&self) -> bool {
48        *self == CLK_SRC_SEL_A::HOSC
49    }
50    #[doc = "`1`"]
51    #[inline(always)]
52    pub fn is_pll_video0_1x(&self) -> bool {
53        *self == CLK_SRC_SEL_A::PLL_VIDEO0_1X
54    }
55    #[doc = "`10`"]
56    #[inline(always)]
57    pub fn is_pll_video1_1x(&self) -> bool {
58        *self == CLK_SRC_SEL_A::PLL_VIDEO1_1X
59    }
60    #[doc = "`11`"]
61    #[inline(always)]
62    pub fn is_pll_peri_1x(&self) -> bool {
63        *self == CLK_SRC_SEL_A::PLL_PERI_1X
64    }
65}
66#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
67pub type CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLK_SRC_SEL_A>;
68impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    #[doc = "`0`"]
74    #[inline(always)]
75    pub fn hosc(self) -> &'a mut crate::W<REG> {
76        self.variant(CLK_SRC_SEL_A::HOSC)
77    }
78    #[doc = "`1`"]
79    #[inline(always)]
80    pub fn pll_video0_1x(self) -> &'a mut crate::W<REG> {
81        self.variant(CLK_SRC_SEL_A::PLL_VIDEO0_1X)
82    }
83    #[doc = "`10`"]
84    #[inline(always)]
85    pub fn pll_video1_1x(self) -> &'a mut crate::W<REG> {
86        self.variant(CLK_SRC_SEL_A::PLL_VIDEO1_1X)
87    }
88    #[doc = "`11`"]
89    #[inline(always)]
90    pub fn pll_peri_1x(self) -> &'a mut crate::W<REG> {
91        self.variant(CLK_SRC_SEL_A::PLL_PERI_1X)
92    }
93}
94#[doc = "Field `clk_gating` reader - Gating Clock"]
95pub type CLK_GATING_R = crate::BitReader<CLK_GATING_A>;
96#[doc = "Gating Clock\n\nValue on reset: 0"]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98pub enum CLK_GATING_A {
99    #[doc = "0: `0`"]
100    OFF = 0,
101    #[doc = "1: `1`"]
102    ON = 1,
103}
104impl From<CLK_GATING_A> for bool {
105    #[inline(always)]
106    fn from(variant: CLK_GATING_A) -> Self {
107        variant as u8 != 0
108    }
109}
110impl CLK_GATING_R {
111    #[doc = "Get enumerated values variant"]
112    #[inline(always)]
113    pub const fn variant(&self) -> CLK_GATING_A {
114        match self.bits {
115            false => CLK_GATING_A::OFF,
116            true => CLK_GATING_A::ON,
117        }
118    }
119    #[doc = "`0`"]
120    #[inline(always)]
121    pub fn is_off(&self) -> bool {
122        *self == CLK_GATING_A::OFF
123    }
124    #[doc = "`1`"]
125    #[inline(always)]
126    pub fn is_on(&self) -> bool {
127        *self == CLK_GATING_A::ON
128    }
129}
130#[doc = "Field `clk_gating` writer - Gating Clock"]
131pub type CLK_GATING_W<'a, REG> = crate::BitWriter<'a, REG, CLK_GATING_A>;
132impl<'a, REG> CLK_GATING_W<'a, REG>
133where
134    REG: crate::Writable + crate::RegisterSpec,
135{
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn off(self) -> &'a mut crate::W<REG> {
139        self.variant(CLK_GATING_A::OFF)
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn on(self) -> &'a mut crate::W<REG> {
144        self.variant(CLK_GATING_A::ON)
145    }
146}
147impl R {
148    #[doc = "Bits 0:4 - Factor M"]
149    #[inline(always)]
150    pub fn factor_m(&self) -> FACTOR_M_R {
151        FACTOR_M_R::new((self.bits & 0x1f) as u8)
152    }
153    #[doc = "Bits 24:26 - Clock Source Select"]
154    #[inline(always)]
155    pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
156        CLK_SRC_SEL_R::new(((self.bits >> 24) & 7) as u8)
157    }
158    #[doc = "Bit 31 - Gating Clock"]
159    #[inline(always)]
160    pub fn clk_gating(&self) -> CLK_GATING_R {
161        CLK_GATING_R::new(((self.bits >> 31) & 1) != 0)
162    }
163}
164impl W {
165    #[doc = "Bits 0:4 - Factor M"]
166    #[inline(always)]
167    #[must_use]
168    pub fn factor_m(&mut self) -> FACTOR_M_W<TVD_CLK_SPEC> {
169        FACTOR_M_W::new(self, 0)
170    }
171    #[doc = "Bits 24:26 - Clock Source Select"]
172    #[inline(always)]
173    #[must_use]
174    pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<TVD_CLK_SPEC> {
175        CLK_SRC_SEL_W::new(self, 24)
176    }
177    #[doc = "Bit 31 - Gating Clock"]
178    #[inline(always)]
179    #[must_use]
180    pub fn clk_gating(&mut self) -> CLK_GATING_W<TVD_CLK_SPEC> {
181        CLK_GATING_W::new(self, 31)
182    }
183    #[doc = r" Writes raw bits to the register."]
184    #[doc = r""]
185    #[doc = r" # Safety"]
186    #[doc = r""]
187    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
188    #[inline(always)]
189    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
190        self.bits = bits;
191        self
192    }
193}
194#[doc = "TVD Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tvd_clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tvd_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
195pub struct TVD_CLK_SPEC;
196impl crate::RegisterSpec for TVD_CLK_SPEC {
197    type Ux = u32;
198}
199#[doc = "`read()` method returns [`tvd_clk::R`](R) reader structure"]
200impl crate::Readable for TVD_CLK_SPEC {}
201#[doc = "`write(|w| ..)` method takes [`tvd_clk::W`](W) writer structure"]
202impl crate::Writable for TVD_CLK_SPEC {
203    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
204    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
205}
206#[doc = "`reset()` method sets tvd_clk to value 0"]
207impl crate::Resettable for TVD_CLK_SPEC {
208    const RESET_VALUE: Self::Ux = 0;
209}
d1_pac/ccu/tvd_clk.rs

d1_pac/ccu/
tvd_clk.rs
